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The interests in various emerging memories are rapidly increasing. Among the emerging memories, only STT-RAM and ZRAM show the similar performance to DRAM, in terms of write endurance and write speed. They should be potential candidates for DRAM application, since many outstanding results have been demonstrated recently in spite of the fairly new technology. Nevertheless, the technical maturity and...
A technique for in-situ measurement of process variation in deep trench capacitance, bitline capacitance, and device threshold voltage in embedded DRAM arrays is presented. The technique is used to directly measure the parameter statistics in two product representative 45-nm SOI eDRAM arrays.
This paper presents a 1.7 ns-random-cycle SOI embedded-DRAM macro developed for the POWER7?? high-performance microprocessor and introduces enhancements to the micro-sense-amplifier (??SA) architecture. The macro enables a 32 MB on-chip L3 cache, eliminating delay, area and power from the off-chip interface.
Process variation poses a threat to the performance and reliability of the 6T SRAM cell. Research has turned to new memory cell designs, such as the 3T1D DRAM cell, as potential replacement designs. If designers are to consider 3T1D memory architectures, performance models are needed to better understand memory cell behavior. We propose a decoupled approach for collecting Monte Carlo HSPICE data,...
An application that takes advantage of FeRAM characteristics is replacing current DRAM, which then becomes high-performance nonvolatile RAM cache. This improves system performance for many kinds of computer systems, including mobile PCs, cellular phones, digital video products, and storage systems such as SSDs. However, the highest capacity in nonvolatile RAMs that allow frequent cache reads and writes...
We present a 46 nm 6F2 buried word-line (bWL) DRAM technology, enabling the smallest cell size of 0.013 mum2 published to date. The TiN/ W buried word-line is built below the Si surface, forming a low resistive interconnect and the metal gate of the array transistors. We demonstrate high array device on-current, small parameter variability, high reliability and small parasitic capacitances, resulting...
The SRAM-interface High-speed DRAM (SH-RAM) is an embedded DRAM that can replace almost all embedded SRAMs in SoC fabricated by a 65-nm LSTP embedded DRAM process. This paper describes the SH-RAM compiler that realizes a 1.8-ns random cycle time and a 1.5-ns random access time at 512-Kb macro without area penalty by High-speed Bit Line Operation and Data Line Replica Architecture.
Cell array architecture for floating body RAM of 35 nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM.
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
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