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Recent technological advances allowed the word to construct several wearable products that can capture and process the human body bio-signals. The PPG signal becomes one of the most contenders in heart rate monitoring due to their prominent features, flexibility, effectiveness and low costs. This paper present a novel System of PPG Heart rate calculation based on FPGA, using the Pan and Tompkins as...
In this brief, we introduce an architecture for accelerating convolution stages in convolutional neural networks (CNNs) implemented in embedded vision systems. The purpose of the architecture is to exploit the inherent parallelism in CNNs to reduce the required bandwidth, resource usage, and power consumption of highly computationally complex convolution operations as required by real-time embedded...
The toolflow presented in this demo was created to generate CGRA overlay architectures from either algorithm definitions (mainly for evaluation) or from a simple definition format. The output of the toolchain is always the complete definition of the hardware in VHDL and supplemental files providing information regarding the configuration and the interfaces of the created hardware. In the demo, we...
Sophisticated embedded systems are increasingly used in defence, aerospace and avionic industries. They are responsible for control, collision avoidance, pilot assistance, target tracking, navigation and communications, amongst other functions. In this industrial field, High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated and resource consuming for three reasons...
As it optimizes the resource utilization of FPGA over time and space, Dynamic Partial Reconfiguration is an important feature of FPGA. The Internal Configuration Access Port (ICAP) controller is an important part of reconfiguration system with which to access the configuration registers of FPGA. By reducing the resources consumed by ICAP controller, more resources will be available for the reconfigurable...
Implementing self-adaptive embedded systems, such as UV, involves an offline provisioning of the several implementations of the embedded functionalities with different characteristics in resource usage and performance in order for the system to dynamically adapt itself under uncertainties. FPGA-based architectures offer for support for high flexibility with dynamic reconfiguration features. We propose...
The University of Applied Sciences Technikum Wien offers various courses dedicated to electronic engineering and embedded systems hardware & software design. These courses are embedded in various degree programs such as full-time, part-time, and distance learning. The attendees of these courses train their skills and expertise on the basis of labor exercises, assignments, and tasks. Especially...
The Internet of Things has created a need for embedded devices that, despite being battery powered, can perform complex algorithms when needed. To fulfil this need we present the Elastic Node, a hardware platform that combines embedded field programmable gate arrays (FPGAs) with conventional microcontroller units (MCUs). These nodes can adapt their processing resources when their requirements change...
Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing...
Timing analysis in embedded systems has focused mainly on the Worst-Case Execution Time (WCET) in the past. This was (and still is) important to make guarantees for the application of the system in safety critical environments. Today, two reasons call for a slightly changed perspective. Firstly, the complex and often unpredictable internal structure of modern system-on-chip architectures prohibits...
The use of reconfigurable chips such as FPGAs in embedded systems for many runtime applications is limited by large reconfiguration time. Techniques to circumvent this limitation relies on hardware task reuse which preserve certain circuits on the chip. However, the frequent addition and removal of circuits while preserving others on the chip will inevitably lead to fragmentation of its area, in an...
A pre-trained convolutional deep neural network (CNN) is a feed-forward computation perspective, which is widely used for the embedded systems, requires highly power-and-area efficiency. This paper proposes a binarized CNN on an FPGA which treats only binary 2-values∼(+1/-1) for the inputs and the weights. In this case, the multiplier is replaced into an XNOR circuit instead of a dedicated DSP block...
Modern FPGA System-on-Chips (SoCs) combine high performance application processors with reconfigurable hardware. This allows to enhance complex software systems with reconfigurable hardware accelerators. Unfortunately, even when state-of-the-art software security mechanisms are implemented, this combination creates new security threats. Attacks on the software are now possible through the reconfigurable...
Real-time video processing is a challenge in many embedded system applications. They can be general-purpose processor based (software) or Custom single purpose processor based (hardware). Software processor based rely mostly on real-time operating system layer to allow multiple software threads to run concurrently. Hardware processor based don't need these layers because they are not executing any...
This paper presents a fast and cycle accurate simulation environment for early power-performance analysis of multi-threaded applications targeted to symmetric multiprocessing embedded architectures. Our simulation environment leverages the hybrid prototyping technique, where a lightweight emulation kernel performs logical simulation of multiple identical cores on top of a single physical instance...
The template matching is an important technique used in pattern recognition. It aims at finding a given pattern within a frame sequence. Pearson's Correlation Coefficient (PCC) is widely used to evaluate the similarity of two images. This coefficient is computed for each image pixel, which entails a computationally very expensive process. This paper proposes an implementation of the template matching...
Complex computing platforms involving pipelined processors, memory hierarchies, multi-core and many-core architectures are very common nowadays. These approaches require a deep understanding of the underlying hardware and the corresponding programing model to be able to decide which alternative is more suitable, i.e. obtain the best performance at the minimum cost, for a given application. Hence,...
Programmable hardware devices, specifically FPGAs, are increasingly being used in critical applications. State-of-the-art devices use SRAM memory for configuration purposes, which is very sensitive to faults. Previous studies have shown that, the vast majority of the generated errors have a high latency, and that some failures are due to the accumulation of errors. To overcome these threats, manufacturers,...
A FPGA-based embedded system development platform with dual-camera support, named MorFPGA Duo, is presented in this paper. The MorFPGA Duo platform adopts the modular design concept and is capable of a dual core employing the ARM Cortex A9, two channel SDI cameras with Full-HD resolution, versatile built-in peripherals and high expandability to satisfy users' eager needs for state-of-the-art research...
This paper presents an FPGA based real-time lane detection system for automotive applications. To reduce the computational complexity, the conventional Canny-Hough lane detection algorithm is modified for achieving the real-time processing. The prototype design is realized by using the commercialized FPGA platform and the processing rate is enhanced by 41% compared to the previous detection algorithm.
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