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In this paper a hardware-software design of an object tracking system, which uses a moving camera is presented. The solution is implemented on the Zybo development board with the Zynq SoC (System on Chip) device from Xilinx. The object's position is used to control two servomotors, which constitute a pan-tilt mounting of the camera. The proposed system is able to process a 1280 × 720 @ 60 fps video...
In recent wireless networks, end-nodes are capable of detecting the existence of multiple wireless standards. In this context, it becomes very interesting to design an on-line reconfigurable communication system controlled by a Vertical Handover Algorithm (VHA) that allows selecting the best available wireless standard. In this demo, we propose implementing the Partial Reconfiguration (PR) technique...
Today's industrial requirements regarding the ability of embedded devices used for decentralized automation are increasing. Industrial providers of automation equipment strive to make their products and thus, industrial plants, smarter to raise efficiency. This evolution is based on new technologies like machine learning, predictive maintenance, sensor fusion and advanced process controls. These techniques...
A demonstrator has been developed to illustrate the performance of a lightweight fingerprint recognition algorithm based on the feature QFingerMap16, which is extracted from a window of the directional image centered at the convex core of the fingerprint. The algorithm has been implemented into a low-power ARM Cortex-M3 microcontroller included in a Texas Instruments LaunchPad CC2650 evaluation kit...
In this paper a hardware-software abandoned object detection vision system implemented in the Zynq SoC (System on Chip) device is presented. First, the solution was implemented in C++ and run as a bare metal application on the ARM processor core of the Zynq (using floating and fixed-point computations). For the target video stream 1280 χ 720 @ 50 fps (74.25 MHz pixel clock) it reached only 2 fps....
The toolflow presented in this demo was created to generate CGRA overlay architectures from either algorithm definitions (mainly for evaluation) or from a simple definition format. The output of the toolchain is always the complete definition of the hardware in VHDL and supplemental files providing information regarding the configuration and the interfaces of the created hardware. In the demo, we...
Laser triangulation applications are commonly used for industrial quality control. Such algorithms require real-time systems often made of a computing unit close to the image sensor through a short and fast link. Choosing a camera with integrated Field Programmable Gate Array (FPGA) as the computing unit can provide high pipeline and parallel computing adapted to process image in real-time. Moreover,...
Various signal and image processing applications require vast acceleration in order to enable real-time processing and meet constraints in power consumption. On FPGAs these applications can be implemented as application-specific circuit. Although IP cores for various applications exist, even interfacing these usually requires experienced knowledge in hardware design. Using FPGAs or other accelerators...
An accurate and robust lane recognition is a key aspect for autonomous cars of the near future. This paper presents the design and implementation of a robust autonomous driving algorithm using the proven Viola-Jones object detection method for lane recognition. The Viola-Jones method is used to detect traffic cones that are located besides the road as it can be done in emergency situations. The positions...
Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual...
Time-resolved fluorescence (TRF) analysis is considered to be among the primary research tools in biochemistry and biophysics. One application of this method is the investigation of biomolecular interactions with promising applications for biosensing. For the latter context, time-correlated single photon counting (TCSPC) is the most sensitive, hence preferred implementation of TRF. However, high throughput...
For arithmetic circuits, Reduced-Precision Redundancy (RPR) is considered to be a viable alternative to Triple Modular Redundancy (TMR), as it offers significant power reduction. However, efficient implementation and assessment of hardware arithmetic operators with RPR is still a challenge. In this work we propose a lightweight RPR design methodology that exploits the capabilities of modern synthesis...
Low-power GPUs have become ubiquitous, they can be found in domains ranging from wearable and mobile computing to automotive systems. With this ubiquity has come a wider range of applications exploiting low-power GPUs, placing ever increasing demands on the expected performance and power efficiency of the devices. The LPGPU2 project is an EU-funded, Innovation Action, 30-month-project targeting to...
In this paper we present a novel close-to-sensor computational camera design. The hardware can be configured for a wide range of autonomous applications such as industrial inspection, binocular/stereo robotic vision, UAV navigation/control and biological vision analogues. Close coupling of the image sensor with computation, motor control and motion sensors enables low latency responses to changes...
In recent years, there has been an increasing growth of using vision-based systems for tracking the players in team sports to evaluate and enhance their performance. Vision-based player tracking has high computational demands since it requires processing of a huge amount of video data based on the utilization of multiple cameras with high resolution and high frame rates. In this paper, we present...
Synchronous Dataflow (SDF), a popular subset of the dataflow programming paradigm, gives a well structured formalism to capture signal and stream processing applications. With data-parallel architectures becoming ubiquitous, several frameworks leverage the SDF formalism to map applications to parallel architectures. But, these frameworks assume that the Synchronous Dataflow graphs (SDFGs) under consideration...
3D ultrasound (US) acquisition acquires volumetric images, thus alleviating a classical US imaging bottleneck that requires a highly-trained sonographer to operate the US probe. However, this opportunity has not been explored in practice, since 3D US machines are only suitable for hospital usage in terms of cost, size and power requirements. In this work we propose the first fully-digital, single-chip...
In recent years, Deep Neural Networks (DNNs) have been of special interest in the area of image processing and scene perception. Albeit being effective and accurate, DNNs demand challenging computational resources. Fortunately, dedicated low bitwidth accelerators enable efficient, real-time inference of DNNs. We present an approximate evaluation method and a specialized multiplierless accelerator...
When designing a Multi-Processor System-on-Chip (MPSoC), a very large range of design alternatives arises from a huge space of possible design options and component choices. Literature proposes numerous Design-Space-Exploration (DSE) approaches thats mainly focus on cost optimization. In this paper, we present a DSE approach which focuses on the reliability of the whole design. This approach is based...
In this paper, two novel hardware architectures based on tabled asymmetric numeral systems decoding algorithm are proposed. In the proposed architectures the decoding throughput is highly dependent on the how much the data is compressed at encoding time. The synthesis results presented here show that the throughput of the parallel architecture can reach up 200 MB/s. The benchmarks show that the parallel...
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