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A high order curvature-compensated CMOS bandgap voltage reference(BGR) is presented in TSMC 0.35μm CMOS technology with low power low temperature-coefficient(TC) and high power supply rejection ratio(PSRR). The design is used in low dropout regulators which is applied in implanted chips. TC is compensated by adjusting resistor ratio which have different temperature characteristics. A PSRR enhance...
Forthcoming CMOS technology nodes are in principle sufficient for achieving both the quantum information density and the speed that are critical for error-free logical qubits. Using data from the roadmap for semiconductor devices from ITRS and IEDM, we applied the standard CMOS design rules to a universal set of quantum logic gates to control silicon qubits. We consequently obtain a scaling law for...
Physically Unclonable Functions (PUFs) offer enticing possibilities to incorporate hardware-based security on semiconductor device level. In order to make efficient use of PUF functionality in lightweight cryptographic applications, a low-overhead implementation in terms of chip area and power consumption is required. In this paper a fully differential readout circuit is proposed that allows the generation...
Based on ITRS predictions the existing CMOS Technology that has dominated IC industry for many decades is about to reach its physical scaling limit shortly [1]. Literature available online from various sources is sufficient to justify the limitations of CMOS technology below 22nm. These limitations include Symmetry problems, short channel effects, rise in quantum tunneling/ leakage current, increase...
In this paper, we present an 880 MHz common-drain power amplifier (CDPA) in 130 nm CMOS technology. New PA topologies are required to address the issues of linearity, reliability, and efficiency. The CDPA is one such promising topology. Owing to the inherent feedback nature of a CDPA, the output voltage is a replica of input voltage, thus making the CDPA a highly linear amplifier with good efficiency...
In this paper, we present an 880 MHz common-drain power amplifier (CDPA) in 130 nm CMOS technology. New PA topologies are required to address the issues of linearity, reliability, and efficiency. The CDPA is one such promising topology. Owing to the inherent feedback nature of a CDPA, the output voltage is a replica of input voltage, thus making the CDPA a highly linear amplifier with good efficiency...
This paper introduces the recent development of GaN HEMT track-and-hold sampling circuits (THSCs) with a digital post-correction (DPC) technique for emerging applications. Compared to THSCs in silicon technologies, GaN THSCs achieve 20–30 dB higher signal-to-noise ratio (SNR) for a given bandwidth. Nevertheless, GaN THSCs suffer from dynamic nonlinearity due to charge trapping and introduce low-frequency...
This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative capacitance effect. In hysteretic devices, subthreshold slope as steep as 10mV/dec is achieved in the region where the ferroelectric represents an...
A CMOS Super class-AB transconductor using Quasi Floating Gates (QFG) techniques to improve the speed and slew rate is presented. The QFG technique is applied to a static DC current source in the classic class-AB OTA, boosting the bias current for large input voltages. The new proposed OTA consumes the same static power as the traditional OTA, however the chip area is increased by 8.5% due to the...
A scheme to achieve simultaneously extremely high slew rate improvement and avoiding open loop gain degradation in one stage super class-AB op-amps is introduced. It overcomes the serious shortcoming of super class-AB OTAs that show very high output current enhancement factors at the expense of degrading the open loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain...
In this paper, a time-mode resonator is presented that is used to realize a second-order bandpass ΔΣ time-to-digital converter (TDC). The resonator is constructed as a cascade of two lossless discrete-time integrators implemented using time-latches and some digital logic in a negative feedback configuration. This paper presents for the very first time the means in which time-mode circuits are used...
This paper presents a design of an on-chip single event transient (SET) pulse width measurement system. The proposed system has been designed and implemented in IHP's 250 nm bulk CMOS technology and is intended for evaluation of SET effects in standard digital library cells. It is composed of an inverter-based target circuit, a pulse stretcher and a processing unit for counting the SET pulses and...
A new technique of Ripple carry adder using majority gate based CMOS output wired logic is implemented. The ripple carry adder consists of four Full adder blocks. The carry from each stage is fed to the next stage as carry input. The Sum and carry outputs are obtained using output wired CMOS logic based majority gate. The number of transistors used in the proposed circuit design is less as compared...
There is a growing interest among universities and industry in the field of nano, micro and cube Satellites. These are very small satellites, about the size of a shoebox, which can be launched into space at a much lower cost than typical large satellites. CubeSats are generally low earth orbit-LEO-satellites, which mean they orbit are from 200 to 1200 km above earth surface. Due to the small nature...
This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design in CMOS technology, particularly I4T, 0.35 μm, 45 V, used in automotive industry for sensor application. There are the individual analogue components of the SAR-DAC descibed in this paper: the Comparator, the R-2R Digital to Analog Converter (DAC) and the Operational Amplifier (OPA). The functionality...
According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM>8kV) and good turn-on efficiency...
A high-performance and energy-efficient 256-bit CMOS priority encoder is presented and realized on transistor level using 32 nm predictive technology. The new circuit is designed with a full custom approach and incorporates 2 novel logic styles: the Multiple-Output Monotonic CMOS (M2CMOS) and the Dynamic Inversion technique (DI). The achieved performance is in the order of O(log2(N)), with respect...
This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent Vth controllability. Low-temperature operation enables higher drive...
In this paper, we propose a new complementary topology which could reduce the variability of the cells and offer new topologies with better performances. Using the unique advantage of FDSOI technology “back-gate control”, the complementary structure cross coupled inverters offering a fully symmetrical operation of complementary signals. It offers new solutions and new circuit structures of building...
This paper discusses the industrial and research status of CMOS and CMOS-like commercial and emerging technologies. Effects of scaling on transistor cost, max. system complexity and performance are discussed. Performance of state-of-the-art CMOS VLSI systems is power-constrained. To discuss various existing and emerging technologies, a model of an abstract, technology-independent ideal switch is proposed...
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