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In the via-middle process of 3-D integrated circuit manufacturing, through-silicon via (TSV) annealing causes mechanical stress not only to its surrounding structures, including liner and landing pad, but also the contacts nearby. This process may result in a noticeable pop-out in TSVs and/or contacts, thus complicating the subsequent chemical mechanical polishing (CMP). In addition, residual stress...
A large thermal-mechanical stress caused by the mismatch of thermal expansion coefficients (CTEs) between the copper and silicon substrate occurs in the active area of the stacked 3D device using the through-silicon via (TSV). Therefore, the study of TSV-induced stress is of fundamental importance in our understanding of the keep-out zone (KOZ). We investigated the metal-oxide-semiconductor field-effect...
Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). This work provides solutions to new challenges related to 3D test content, test access, diagnosis and debug. We analyze the the impact...
Due to mismatch in the coefficients of thermal expansion of silicon and copper, mechanical stresses in surrounding silicon are induced near TSV in 3D ICs. In this paper, the mobility variance of substrate material caused by TSV-induced stress is researched. Firstly the semi-analytical model for TSV-induced stress distribution is introduced. An analytical model for TSV-induced stress distribution is...
Due to mismatch in the coefficients of thermal expansion of silicon and copper, mechanical stresses in surrounding silicon are induced near TSV in 3D ICs. In this paper, the mobility variance of substrate material caused by TSV-induced stress is researched. Firstly the semi-analytical model for TSV-induced stress distribution is introduced. An analytical model for TSV-induced stress distribution is...
In this paper we use finite element simulations to determine the influence of two key design parameters on the thermomechanical stress and the stress interplay in copper-filled TSV arrays. The two parameters are the via's pitch-to-diameter ratio and thickness-to-radius (aspect) ratio. Our analytical results has suggested that the in-plane stress interplay becomes insignificant when the TSV pitch is...
Thermo-mechanical stress due to TSV fabrication processes is a major concern in 3D integration. TSV stress not only degrades the mechanical reliability of 3D ICs but it also affects the electrical properties, such as electron and hole mobility, of the MOS devices surrounding TSVs. Variations in carrier mobility result in a change in the timing profile of the circuit, which has an impact on delay-fault...
The inter-die signal interfaces in a 3D-IC are vulnerable to over-voltage stress induced by Charged Device Model ESD. The magnitude of the stress is highly sensitive to the design of the ground distribution network on both the die and package level. It is also affected by the type of package being used. Small voltage clamping devices may be placed at inter-die receivers to mitigate the risk of gate...
In this work, we propose an efficient and accurate full-chip thermo-mechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermo-mechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the...
Three dimensional integration complements semiconductor scaling; it enables a higher integration density as well as heterogeneous technology integration. Using 3D chip stacking, it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling. The 3D strata may be realized using advanced CMOS technology nodes but may also exploit a wide variety...
Through-Silicon Vias (TSVs) have recently aroused much interest because it is a key enabling technology for three-dimensional (3-D) integrated circuit stacking and silicon interposer technology. In this study, a 3-D 1/8th symmetrical nonlinear finite element model of a stack die TSV package was developed using ANSYS finite element simulation code. The model was used to optimize the package for robust...
A new methodology to bridge package and silicon domain simulations is demonstrated using a new data file to facilitate stress information exchange. The flow integration uses equivalent stress conditions to replace sensitive process information and parameterized modules to minimize user interventions for 3D IC stress simulations.
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