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Over the past few years we have articulated theory that describes ‘encrypted computing’, in which data remains in encrypted form while being worked on inside a processor, by virtue of a modified arithmetic. The last two years have seen research and development on a standards-compliant processor that shows that near-conventional speeds are attainable via this approach. Benchmark performance with the...
Code injection attacks are an undeniable threat in today's cyberworld. Instruction Set Randomization (ISR) was initially proposed in 2003. This technique was designed to protect systems against code injection attacks by creating an unique instruction set for each machine, thanks to randomization. It is a promising technique in the growing embedded system and Internet of Things (IoT) devices ecosystem,...
Algorithms for data encryption are one of the most important parts of modern communication systems. In this paper the results of hardware implementation of AES256 and TDES algorithms are presented. AES256 and TDES are implemented as an IP core with AXI interface because of constant growth of data transfer requirements in modern embedded systems, in order to improve their capability. Beside details...
We describe a novel key-centric processor architecture in which each piece of data or code can be protected by encryption while at rest, in transit, and in use. Using embedded key management for cryptographic key handling, our processor permits mutually distrusting software written by different entities to work closely together without divulging algorithmic parameters or secret program data. Since...
The cryptographic hash functions BLAKE and Skein are built from the ChaCha stream cipher and the tweakable Threefish block cipher, respectively. Interestingly enough, they are based on the same arithmetic operations, and the same design philosophy allows one to design lightweight coprocessors for hashing and encryption. The key element of our approach is to take advantage of the parallelism of the...
Ubiquitous information exchange and processing require low cost and secure cryptographic primitives. RC4 is one of the most popular stream ciphers with well-known strengths and weaknesses. Though it is primarily designed as a software stream cipher, recent results show that it can be implemented on a small area with encryption speed matching that of hardware-oriented stream ciphers. An accelerator...
The reconfigurable processors like FPGA are extensively used for cryptographic applications which have reduced the time to market of the hardware logic. This paper describes the high performance pipelined hardware implementation of RC5 algorithm in Xilinx Vertex II Pro FPGA with a 12-stage pipeline scheme that has achieved an encryption rate of 6.9 Gbps. The proposed design operates on 12 input data...
Pipelined S-boxes are usually used in high speed hardware implementations of the Advanced Encryption Standard (AES), and not typically found in compact implementations because of the extra complexity added by the pipeline registers. In this paper, the area and speed performance of applying a pipelined S-box to compact AES hardware implementations is examined. A new compact AES encryption hardware...
This paper analyzes algorithmic characteristics of AES Encryption/Decryption, and proposes a design methodology for AES algorithm digital hardware circuit through integrating the technologies of pipeline and parallel connections with dynamic reconfiguration. And a dynamic reconfiguration circuit model was built to test out the design methodology. The results of simulation and verification experiments...
Recently, DES has been the most widely used symmetric block cipher for information security. But many powerful attacks, such as differential attack and linear attack had been proposed for cryptanalyzing DES. This paper gives an introduction and theoretical analysis of DES Algorithm and proposes a new design of encryption key and S-box to improve the algorithm performance. The hardware language VHDL...
The article presents a pipeline implementation of the block cipher CLEFIA. The article examines three known methods of implementing a single encryption round and proposes a new fourth method. The article proposes the implementation of a key scheduler, which is highly compatible with pipeline encryption. The article contains a detailed analysis of the data processing path for the 128-bit key version...
A novel programmable security processor for cryptography algorithms is presented in this paper. The 16-bit length RISC-like instruction set and 3-stage pipeline provide low code density, low hardware cost and low power consumption. Parallel on-chip lookup tables are integrated to obtain satisfactory performance of cryptographic processing. Chinese wireless local area network block cipher standard-SMS4...
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