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In situ lift out is a mature and well established technique for TEM sample preparation [1]. There are occasions though, when lift out fails, and the TEM lamella falls into the TEM trench during sample preparation. In a previous study [2], the lamella can be rescued through a series of steps involving welding, tilting, cutting free and rewelding the lamella onto a grid or die. In this paper, we detail...
In this paper, we reported a EVB Burn In (B/I) failed case of our ABCD part and led to the finding of VIA process fabrication issue with TiN film process marginal issue. This EVB B/I failed case was carried out by electrical failure analysis (EFA) and physical failure analysis (PFA) using FIB X-section and TEM. This paper also demonstrated different EFA technology, which included curve tracer analysis,...
Focused Ion Beam, also known as FIB, is a technique that widely used in semiconductor field. The common purpose is to do circuit modification, layout verification, micro-circuit failure analysis, mask repair and Transmission Electron Microscope (TEM) specimen preparation of site specific locations [1]. Backside fault isolation is a method to get optimum transmission and localized failure site. Fault...
The clamped inductive turn-off failure of Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor (SOI-LIGBT) with multi-finger layout pattern is investigated in this paper. Firstly, the measurements of device failure under clamped inductive turn-off are discussed. Secondly, simulations are carried out to reproduce the failure by using Sentaurus TCAD. It is found that the failure origins from...
Scanning microwave impedance microscopy (sMIM) is an emerging electrical mode for scanning probe microscopy (SPM). We apply the technique to the profiling of dopants in semiconductor samples with sub-micron spatial resolution. This work demonstrates the practical application of sMIM for quantitative measurement of the dopant concentration profile in production semiconductor devices. A planar dopant...
Failure Analysis (FA) consists of fault verification, isolation, defect tracing, characterization and physical (elemental) analysis. It helps wafer fab to understand the root causes of low yield cases, drive the yield improvement activities. Due to the complexity of modern Integrated Circuits (ICs), defects causing the failure need more effort, a variety of FA tools to be identified. In this case,...
As the applications of micro electronic mechanical system (MEMS) are booming, more and more research and development activities are involved in the MEMS industry. For every new MEMS product with new functions, the manufacturing process will be tailored to cope with the changes. This requires reliability work to ensure the robustness of the new process. Thus, failure analysis plays an important role...
In this paper, a new and simple method named Weibull criterion is proposed to identify whether metastable states occur in single random telegraph noise (RTN), which has been verified by both simulation and experiment results. It is helpful for comprehensive understanding of trap properties and providing a direct evidence of oxide traps with multiple states.
Electrochemical migration (ECM) pose a high reliability risk to semiconductor devices. In this study, an ECM caused electrical failure case detail was shared, relevant electrical failure & ECM mechanism was also analyzed. To verify the failure mechanism discussed in this paper, ECM process was simulated on the same chip substrate. Besides, for the first time, the effect of chloride ion concentration...
High Power Diodes are essential elements for electronics systems. During their operation, high Thermal Resistance will account for electrical characteristic degradation, affecting the operation of electronics systems. Hence an effective method to screen the devices with high thermal resistance is required. ΔVf test is known to be a suitable method for screening out the devices with poor solder quality...
Based on the Meyer-Neldel Rule (MNR), analytical drain current model is presented for the polycrystalline ZnO thin-film transistors at different temperatures. The MNR-based drain current model is developed from the surface-potential-based model considering the effective medium approximation (EMA). Applying the Meyer-Neldel Rule, the drain current model is developed. The model results are in agreement...
As the process of device is scaling down continually. Engineers are trying their best to challenge the limitations of physics in IC industry. However, power IC like power MOSFET and Insulated Gate Bipolar Transistor (IGBT) still have a high requirement despite device scale — downs. Here, we want to highlight a method to improve defect location in IGSS (Gate — Source leakage) failure, through this...
Being an advanced application of SEM based Nanoprobing tool, Electron Beam Current (EBC) is commonly applied for detecting test-key failure or LBIST scan failure. In this paper, EBC is employed with TIVA (Thermal Induced Voltage Alteration) to diagnose the chip level Pin high resistance failure related issue.
This paper reports characterization and analysis of diode string electrostatic discharging (ESD) protection structures fabricated in a foundry 28nm CMOS technology. Comprehensive measurements were conducted using very-fast transmission line pulse (VFTLP) tester for Charged Device Model (CDM) ESD protection. The analysis results reveal the I-V insights critical to practical ESD protection designs.
An analytical model for the conduction characteristics of commercially available light-emitting diodes (LED) subjected to severe degradation conditions is reported. The devices were stressed at different temperatures in the range from 27°C to 80°C using high-current (80mA) accelerated life-tests. First, a modified compact model for the fresh I-V characteristic of the devices is presented. Instead...
In this study, we introduce high-resolution X-ray tomography into the daily failure analysis (FA) work flow for semiconductor packages. Two application cases, the investigation of Back-end of line (BEOL) and μ-bump features have been selected to demonstrate its advantage. The paper focuses on a feasibility study for different measurement parameters and proposes an advanced FA flow including newly-developed...
Thin film deposition process invariably introduces compressive or tensile stress in the films. The stress in a film causes the wafer to warp whose curvature is estimated in a wafer fab using optical reflectance technique. Alternatively, the wafer curvature can also be measured using the high resolution XRD (HRXRD) Si(004) rocking curves. In this paper, the HRXRD technique was employed to evaluate...
A simulation study is conducted to model the behavior of the MOS transistor output response with a resistive defect on gate, with both DC and pulse signal inputs. Nanoprobing is performed on actual transistors in DC and pulse modes to validate the simulation. Compared to a reference transistor, a more resistive gate corresponds to a larger rise time in the dynamic pulse response, while the static...
This paper describes the analysis approach and methodology when dealing with Digital Quiescent current (IDDQ) most common issue, a vector dependency current drift. A typical Design for Testability (DFT) test structure are used as vehicle to exemplified the approaches that used in the lab scale that probably be the ultimate solution to overcome limitation on most of the lab. A special analysis flow...
Failure analysis on static condition (static leakage and standby current level) failed device would not cost long time to find root cause, but dynamic functional failure will. Failure analysis with dynamic strategy to localize a failure point is more significant in complicated function failed IC (Integrated Circuit). This paper would present an efficient strategy to locate the defect using dynamic...
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