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This paper reports characterization and analysis of diode string electrostatic discharging (ESD) protection structures fabricated in a foundry 28nm CMOS technology. Comprehensive measurements were conducted using very-fast transmission line pulse (VFTLP) tester for Charged Device Model (CDM) ESD protection. The analysis results reveal the I-V insights critical to practical ESD protection designs.
An analytical model for the conduction characteristics of commercially available light-emitting diodes (LED) subjected to severe degradation conditions is reported. The devices were stressed at different temperatures in the range from 27°C to 80°C using high-current (80mA) accelerated life-tests. First, a modified compact model for the fresh I-V characteristic of the devices is presented. Instead...
Failure analysis on static condition (static leakage and standby current level) failed device would not cost long time to find root cause, but dynamic functional failure will. Failure analysis with dynamic strategy to localize a failure point is more significant in complicated function failed IC (Integrated Circuit). This paper would present an efficient strategy to locate the defect using dynamic...
The effects of fast neutron radiation up to flux of 1014 cm−2 (1 MeV equivalent flux) upon the turn-on and forward static characteristics of MOS-Controlled Thyristor (MCT) are described in this work, based on physics-based 1-dimension analytical calculation and 2-dimension Silvaco simulation. It is reported for the first time that dependency of on-state specific resistance (Ron) upon neutron flux...
A SPICE-level aging simulation methodology is developed to predict the NBTI degradation in short term and long term region. This methodology enables 10 years NBTI aging prediction under any bias conditions (including stress and recovery) by completing the time-tracing and extrapolation procedures in a single step. The proposed methodology significantly improves the speed of the long term simulation...
Lack of accurate ESD device models and CAD methods makes on-chip ESD protection circuit design optimization and verification impossible. This paper reports a new circuit-level ESD protection simulation method using ESD behavior models to quantitatively analyze the ESD discharging functions at chip level, including checking the transient node voltage and branch current on a chip during ESD events....
A novel 2×VDD-tolerant electrostatic discharge (ESD) detection circuit which uses only low-voltage devices is proposed in a 0.18 um CMOS process. Under normal operating conditions, all the devices are free from over-stress voltage threat. Our proposed detection circuit achieves a high triggering efficiency with a much smaller footprint. Comparing with the RC based detection circuit, our proposed circuit...
A failure analysis of a product due to the on chip ESD structure defects is presented in this paper. ESD is one of the most important reliability issues in the design of integrated circuits. About 40% of the failure of integrated circuits is related to ESD/EOS stress. In order to improve the reliability of ICs, the design of ESD protection is increasingly necessary for the modern semiconductor industry...
Forward body bias method for evaluating total ionizing dose (TID) effect in deep sub-micron CMOS integrated circuits is proposed. Without traditionally complicated, time consuming and costly transistor radiation modeling or chip irradiation test, it is demonstrated here that by applying equivalent forward body bias on susceptible NMOS transistors, TID effect evaluation for deep sub-micron CMOS ICs...
SRAM-based FPGA has become a core device in space application. However, based on CMOS technology, SRAM-based FPGA is sensitive for SEU effect. JTAG circuit is a significant module of SRAM-based FPGA, executing boundary-scan test and global configuration function. SEU effect can result in function disturbance of JTAG circuit. To adopt reasonable harden strategies for JTAG circuit, the paper puts forward...
Photon Emission Microscopy is the most widely used mainstream defect isolation technique in failure analysis labs. It is easy to perform and has a fast turnaround time for results. However, interpreting a photon emission micrograph to postulate the suspected defect site accurately is challenging when there are multiple abnormal hotspots and driving nets involved. This is commonly encountered in dynamic...
Modeling the negative bias temperature instability (NBTI) can optimize circuit design. Several models have been proposed and all of them can fit test data well. These models are extracted typically by fitting short accelerated stress data. Their capability to predict NBTI aging outside the test range has not been fully demonstrated. This predictive capability for long term aging under low operation...
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