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In this paper, a method to detect shorts at the gates of the storage node of a 6T SRAM bit cell via atomic force probing (AFP) at the Via 1 level is discussed. This method is useful for the preservation of physical evidence as well as to ease the probing operation due to the lower density and larger separations of vias compared to contacts. One particular case of single bit failure is documented,...
In this paper, a novel signal toggling technique in Electrical Optical Frequency Mapping/ Phase Mapping (EOFM/EOPM) and Electrical Optical probing (EOF) are performed to successfully localized the fault location and identify the physical defect promptly. A function square wave is asserted into the pin of interest, i.e. leakage pin or the function power pin, for EOFM and EOF purposes. This technique...
This paper describes the analysis approach and methodology when dealing with Digital Quiescent current (IDDQ) most common issue, a vector dependency current drift. A typical Design for Testability (DFT) test structure are used as vehicle to exemplified the approaches that used in the lab scale that probably be the ultimate solution to overcome limitation on most of the lab. A special analysis flow...
As the development of semiconductor process, more and more advanced technologies were applied in the IC manufacturing. The device becomes more precise, and more sensitive to the minor process variation. Failure analysis challenge comes along with these advanced processes. Lithography process is one of the most critical semiconductor processes. The issue with this process has its own property. Based...
In this work, ESD immunity enhancement for the HV n-channel LDMOS with source-end discrete islands fabricated by a TSMC 0.25 μm 60 V process was investigated. An nLDMOS device always has poor ESD capability. If discrete n+ islands are formed in the source end of an nLDMOS transistor, the It2 value of this DUT is upgraded by 4.92% as compared with that of the reference nLDMOS. Meanwhile, if an nLDMOS...
Demand of short failure analysis has been increasing in semiconductor failure analysis. It is known from the previous studies that many short failure analysis methods are suggested. However, it is extremely difficult to identify the short failure location in recent advanced devices due to the fact of optical resolution limit. On the other hand EBAC has been noted as the high resolution method to identify...
This paper highlights systematic fault isolation approaches to identify back-end of line metal bridging through the combination of techniques such as photon emission, soft defect localization, laser voltage probing as well as combinational logic analysis, to successfully pin point a single metal layer for physical failure analysis, thus boosting the overall success rate and turnaround time.
SRAM is a major component in semiconductor industry which often requires extensive and exhaustive method of fault isolation, especially for a non-visual defect in a soft failure mode. For these cases, nanoprobing on CA layer is often performed but there are times when it fails to isolate any defect. One reason may be because the failure only occurs at high temperature test environment. This paper...
In this study, we implemented the backside PLS (Photoelectric Laser Stimulation) based circuit edit on an analog circuit block of a mixed-signal IC (Integrated Circuit). In this technique, a laser with the wavelength in the NIR (Near Infrared) range is employed to optically stimulate the DUT (Device under Test) at the transistor level, and impact optically its electrical performance including threshold...
We present a comprehensive study of electro-optical frequency mapping (EOFM) and probing (EOP) on NAND and NAND-like structures with different sizes. Our main objective was to find out, if it is possible to detect single dysfunctional transistors in a NAND structure smaller than the laser spot just by means of the optical signal. We further investigate the impact of parasitic laser voltage signals...
ESD protection design for the RF transmit/receive switch (T/R switch) with embedded silicon-controlled rectifier (SCR) is proposed, where the SCR device is embedded in the ESD diode and the transistors of T/R switch by layout skill. Silicon chip verified in a 90-nm CMOS process has been measured by TLP and HBM ESD test to confirm its efficiency for ESD protection. The parasitic capacitance from the...
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