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Wafer level chip scale package (WLCSP) devices have seen significant growth and demand in the recent years largely driven by the mobile consumer market. WLCSP offers significantly reduced package footprint, high electrical and thermal performance, and lower cost of manufacturing. After the initial qualification of the device, an ongoing reliability monitor program is critical in ensuring the continued...
In this paper, we performed accelerated degradation testing (ADT) of a certain type of driver IC under different humidity stress levels. We keep the drivers in storage under same temperature but different humidity; measure the determined sensitive parameter of the driver with fixed time interval, then model the degradation path to obtain the pseudo-failure lifetime. Finally, we analyze the test data...
RF Power amplifier often demands Zero-defect in application. However, it sees non-uniform stress during application. The time depend stress level depends on the input signals. This paper presents a way to predict the gate oxide lifetime, not only for the intrinsic oxide breakdown, but also for the extrinsic oxide breakdown. An appropriate gate oxide screening condition would enable the desired quality...
In this study, we found that inappropriate TU (top Cu metal line) geometry design induced product reliability failures issue. The TU geometry, having poor compatibility with wafer test probe issue, couldn't withstand the stress of wafer test probe resulting in fractures. Due to the inappropriate TU geometry design had major disadvantages in circuits characteristics. Reliability estimations exhibited...
Thin film deposition process invariably introduces compressive or tensile stress in the films. The stress in a film causes the wafer to warp whose curvature is estimated in a wafer fab using optical reflectance technique. Alternatively, the wafer curvature can also be measured using the high resolution XRD (HRXRD) Si(004) rocking curves. In this paper, the HRXRD technique was employed to evaluate...
The solder points cracking of a component with package of ceramic ball grid array (CBGA) type is studied in the paper. The cracking cause is found and the failure mechanism is clarified. The weakness of the package structure design is demonstrated by comparing the experiment results of two kinds of components, which provides guidance for the reliable design and application.
An electrostatic discharge (ESD) protection design by using stacked diodes and silicon-controlled rectifier (SCR) as power clamp is presented to protect a K-band low-noise-amplifier in nanoscale CMOS process. Experimental results show that the proposed design can achieve higher ESD robustness without degrading the radio-frequency (RF) performance. Based on its good performances during ESD stress and...
In this paper, it is reported for the first time that, in nanoscale high-k/metal-gate MOSFETs, the hot carrier degradation (HCD) follows a two-stage law in some stress conditions. Both interface traps and oxide traps contribute to HCD causing its time-dependence varies with different stress modes. The results are helpful for the physical understanding of HCD in nanoscale devices.
A SPICE-level aging simulation methodology is developed to predict the NBTI degradation in short term and long term region. This methodology enables 10 years NBTI aging prediction under any bias conditions (including stress and recovery) by completing the time-tracing and extrapolation procedures in a single step. The proposed methodology significantly improves the speed of the long term simulation...
In this paper, the gated imaging technique of dynamic photon emission is realized and introduced as a powerful localization tool by using a low-cost near-infrared InGaAs image intensifier (I.I). At first, the setup and the method for gated imaging of photon emission microscope (GI-PEM) are presented. As one of global localization tools, it shows an unique and economical debugging and pinpointing capabilities...
The combined benefits of reduced package footprint, higher input/output capability, better power and ground distribution and reduced signal inductance has made the flip chip package technology a primary packaging solution for portable consumer electronics as well as commercial/industrial applications. The technology qualification step ensures the highest quality and reliability performance on devices...
This is a case study of an early failure analysis on a chip fabricated on the 40nm technology node. A large leakage current was observed in the high voltage (HV) supply after the chip was stressed as a part of an early failure rate (EFR) test. Electrical failure analysis (EFA) using Backside Emission spectroscopy [1] and Optical Beam Induced Resistance Change (OBIRcH) [2] showed the existence of hotspots,...
Large scale and high density packaging of ASICs are usually achieved by FCBGA forms. The structure and materials are more complicated in FCBGA, which would cause reliability concerns in situations where thermo-mechanical stressing is dominant. Accelerated temperature cycling reliability test was performed on 90-nm/8-level copper based FCBGA packaging devices, and open failures dominated by thermo-mechanical...
In this study, we investigate the Ron degradation in D-mode AlGaN/GaN MIS-HEMTs on a Si substrate via an accelerated step stress at different temperatures. We have observed a three-phase Ron degradation behavior, which is highly correlated with a drain bias and back gate bias. First, the Ron degradation increases till a peak value when the drain bias increases. Second, when the drain bias increases...
A failure analysis of a product due to the on chip ESD structure defects is presented in this paper. ESD is one of the most important reliability issues in the design of integrated circuits. About 40% of the failure of integrated circuits is related to ESD/EOS stress. In order to improve the reliability of ICs, the design of ESD protection is increasingly necessary for the modern semiconductor industry...
In this paper, we present the experimental I-V and C-V characterization of vertical trench DMOS with different gate electrode recess depths. NBTI/PBTI test, via static bias stress test method was also performed in order to identify possible contaminations of the channel region. Effects of increasing this recess depth on the main electrical and capacitance performances are accurately measured. We concluded...
The scope of this paper is to study on corrosion failure mechanism of ceramic optocoupler under thermal stress. With this regard, a failure case for current transfer ratio (CTR) deviates is analyzed. Scanning electron microscopy (SEM) and energy dispersive X-ray microanalysis (EDX) are used to detect the failure position. The SEM study revealed that the passivation layer is the critical factor of...
In the analysis of plastic packaging SiP product failure, we should not only consider the plastic material and techniques inherent problems, but also the problem that SiP products have a lot of materials, complex structure, and small surface bonding. A type of plastic packaging SiP module function failure after reflow soldering, through appearance inspection, pin electrical characteristic test, X-ray...
In view of reducing the process development cycle times with plausible time-to-market goals, it is of great demands to speed up the assessment pace, but at the same time not to jeopardize for the high level of quality requirements. Highly robust designs and process margins are the key differentiators and should be enforced in particular for the automotive markets. In this work, development of the...
In semiconductor manufacturing for automotive as for many other industries, reliability tests are designed and implemented in order to predict failure rate in real life and applications. Physics-of-failure is used on the rejects observed in field and during the reliability tests to check them to stress the components as in life applications. Besides this qualitative study between field and reliability...
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