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A novel IR-aware chip and interposer co-design methodology is presented to handle both chip-interposer routing and micro-bump planning for IR drops. Based on bump rules and power information in a chip, the methodology analyzes the locations of micro bumps to meet IR constraints. For chip-interposer routing, the computational geometry techniques (e.g., Delaunay triangulation and Voronoi diagram) are...
Through silicon via (TSV) is a widely used interconnect technology in 3-D integrated circuits. This paper shows that defective TSVs can induce small delay faults in surrounding logic gates. We present simulation results of TSV-induced small delay fault (TSDF) because of mechanical stress or pinhole leakage. A test technique is proposed to detect TSDF using a physical-aware fault extractor and timing-aware...
This paper presents a novel test generation technique for defective power TSV induced path delay faults in 3D IC. This paper provides a simple close-form analysis to show that, in a regular 3D power grid model, open defects in power TSV do not induce serious IR drop. However, leakage defects in power TSV should be tested, even though the number of power TSV is large. This paper proposes a test generation...
In this paper, a technique to reduce the output jitter and the wide-range operation is presented. A wide-range voltage controlled delay line (WRVCDL) uses multi-band to operate on wide-range. The proposed DLL operates from 25MHz to 250MHz. An edge combiner (EC) is used to increase the output frequency range. It synthesizes frequencies from 250MHz to 2.5GHz. The output of EC will be a 50% cycle in...
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