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In this paper, a technique to reduce the output jitter and the wide-range operation is presented. A wide-range voltage controlled delay line (WRVCDL) uses multi-band to operate on wide-range. The proposed DLL operates from 25MHz to 250MHz. An edge combiner (EC) is used to increase the output frequency range. It synthesizes frequencies from 250MHz to 2.5GHz. The output of EC will be a 50% cycle in...
In this article, a new methodology for mapping applications onto matrix-based nanocomputer architectures is proposed. It takes into account the structural characteristics and connectivity restrictions of cell matrices and can be used (i) for the partitioning and mapping of applications, (ii) for the generation of alternative mapping configurations with required area, power and delay characteristics...
The ultimate goal of this work is to identify a methodical analysis of imager design to achieve high level of flexibility and modularity. It will enable early stages of design space exploration using hierarchical approach. In particular, we develop generic models for imager IC in order to explore early design choices throughout the hierarchy. This modeling approach supports top-down design flows.
Power supply noise and ground bounce can significantly impact the circuit's performance. Existing delay testing techniques do not capture the impact of combined and uncorrelated power supply noise and ground bounce for critical path delay analysis. They capture the worst case power supply noise in order to obtain the worst case path delay. We show that such assumption is not necessarily sufficient...
This paper reports on a voltage controlled ring oscillator fabricated in a 130nm CMOS technology. The oscillator was obtained cascading three delay cells. The schematic of the single delay cell was kept as simple as possible by avoiding the use of cross-coupled pairs. The achieved low phase noise makes the presented ring VCO useful for the design of a correlation radar to be used in medicine for short...
The delay caused by global interconnects plays a critical role in the performance of VLSI circuits, particularly for transmission effects in nano scales. This paper presents an analytical formulation for the delay of tapered partitioning scheme of buffer insertion in long global interconnects. The inductive effects have been taken into account in RLC delay expressions. Because of complexity of the...
The novel topology of the CMOS ring oscillator array is proposed, where the array elements are braided. Compared with the conventional topology of the CMOS ring oscillator array, the proposed oscillator array possesses the nature of the tight and bi-directional connections, and will has the possibility of the phase noise performance improvement. To verify the performance improvement of the proposed...
A novel design of linear-phase sharp FIR filters is presented in a closed form by employing sampling kernels and relationships among half-band filters, Hilbert transformers, and differentiators. Design examples demonstrate that three designed sharp FIR filters (i.e., half-band filter, Hilbert transformer, and differentiator) can be easily and directly obtained with small number of multipliers and...
In this paper, we propose a level shifter circuit capable with a wide input voltage range. The circuit is based on a conventional two-stage comparator, and has a distinctive feature in current generation scheme by monitoring input and output logic levels. The proposed circuit can convert low voltage input digital signals into high voltage output digital signals. The circuit achieves low power operation...
A phase-based delta-sigma analog-to-digital converter (ADC) architecture with a combination voltage-controlled and digitally-controlled delay lines (VCDL-DCDL) is presented. The architecture uses this VCDL-DCDL combination as the phase-domain counterparts of an ADC-DAC in a traditional delta-sigma modulator. Simulation results of the new modulator achieve a 60.1 dB SNR, or a 9.7 bit over a 10 MHz...
In this paper we present a novel ultra-low-voltage (ULV) CMOS flip-flop. The ULV flip-flop offers increased speed compared to other FF's for low supply voltages. The pulse generator (PG) circuit in a conventional sense amplifier SAFF is replaced by a high-speed tristate edge generator (EG) with a rise- and fall-time less than 1/10 of an inverter operating with the same supply voltage. In essence the...
Recently, latch-based design has attracted attention due to its several merits. Time borrowing is one feature of latches, where a slower functional unit can borrow timing slacks from a faster functional unit. This paper shows that latency can be reduced by integrating the time borrowing into operation scheduling in latch-based design. Specifically, continuous execution delay model is adapted to operation...
Reliability becomes one of the most important issues for designing LSIs. Negative bias temperature instability (NBTI) is a phenomenon in which performance of transistors deteriorates depending on temperature and transistor switching frequency. In the manufacturing process generations of 32 nm and 22 nm, it will be expected that timing degradation by NBTI becomes non-ignorable. This research proposes...
The dense routing channels of long global interconnects in today's high performance Field Programmable Gate Arrays (FPGAs), as principle counterpart for ASICs, is a dominant factor in continuous increase in the delay, power, and also the chip area. Using the three dimensional (3D) technology is an essential and also attractive technique to solve these problems. However, the limitation on the number...
A new method for designing non-uniform filter-banks for acoustic echo cancellation is proposed. In the method, the analysis prototype filter design is framed as a convex optimization problem that maximizes the signal to alias ratio (SAR) in the analysis banks. Since each sub-band has a different bandwidth, the contribution to the overall SAR from each analysis bank is taken into account during optimization...
This paper presents a novel approach to evaluate silicon Physically Unclonable Functions (PUFs) implemented in FPGAs and based on delay elements. The metrics studied to characterize the PUFs are Randomness, Uniqueness and Steadiness. They take advantage of the measured physical values of elementary component making up the PUF. The delay distributions provide the interest to quantify the PUF at the...
Voltage reduction is a very widely used low-power technique (as reducing dynamic power quadratically, and leakage power linearly) which does sacrifice performance. An alternate technique, which is much less explored/investigated, is to rely on currents instead. The paper presents a thorough but still preliminary comparison of a recently introduced CMOS design technique which limits/reduces currents,...
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