The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Basing on a bandpass ΔΣ modulator model in superconducting technology, we propose to design and implement a time-interleaved parallel architecture for this type of ADC. The interest of such architecture consists in combining oversampling and time-interleaved techniques in order to obtain a high speed and large band superconducting ΔΣ ADC.
A spread-spectrum clock generator (SSCG) with self-calibration circuit (SCC) is presented in this paper. By the use of self-calibration scheme, exploited the proposed linear circuit and a SCC, the gain of Kvco can be effectively reduced and the jitter performance is improved. Moreover, the proposed architecture provides an alternative technique for low Kvco instead of the commonly used methods for...
This paper concerns production test of analog and RF communication devices. The use of standard digital tester channel for the acquisition of modulated analog/RF signals is investigated in order to implement low-cost functional test. The idea is to use the comparator available in a standard digital test resource to record level-crossing events on a signal coming from the device under test, and then...
This paper presents an all-digital 4-bit delta-sigma (ΔΣ) modulator for envelope elimination and restoration (EER)-based polar transmitters. A fast feedback approach is devised by combining the digital truncator with path gains to reduce the propagation delay of feedback loops in modulators. The CMOS standard cell-based design could hence be utilized to implement the proposed modulator at a sampling...
This paper presents a novel continuous time ΔΣ modulator for multi-mode operation. The design is targeted for low power, low IF multi-mode receivers and could operate on any bandwidth ranging from 0.5MHz to 1.5MHz while using the same architecture. A 3rd order, quadrature bandpass (QBP) modulator is preferred that operates on a single side of the frequency spectrum and hence improves the noise shaping...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.