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MuCCRA-cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90 nm CMOS process consisting of four dies each of which has a 4 times 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and...
Efficient cycle-based reconfiguration of datapaths can be realized on current FPGAs by designing merged datapaths, which can execute different tasks depending on the datapath control. In our previous work, we provided a synthesis tool for the automated generation of such datapaths. The objective in this paper is a reduction of the resource requirements for implementing the reconfiguration control...
Based on the power consumption analysis of a real dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3, it appears that the key of power saving is keeping the datapath on the processing element (PE) array as possible. Fine grain partial reconfiguration (FGPR) is a simple technique to minimize the change of configuration code in a hardware context switching. In FGPR, a configuration...
An important biology problem is the decoding of the DNA and the extraction of useful genetic information. There are many bioinformatics algorithms that try to solve the gene finding problem and one of the most efficient is the Glimmer algorithm. In this paper, we present a hardware architecture that implements the Glimmer algorithm. The architecture was developed specifically for the capabilities...
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