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This paper presents a methodology for estimating and optimising FPGA routing fabrics using high-level modelling and convex optimisation techniques. Experimental methods for exploring design spaces suffer from expensive computation time, which is exacerbated by increased dimensionality due to the larger number of architectural parameters. In this paper we build on previously published work to describe...
As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. The current multi-player, partial-reconfiguration (PR) design flow does not facilitate bitstream-level IP core license enforcement, e.g, time-limited or pay-per-use. This paper proposes the use of a secure reconfigurable controller (SeReCon) for accounting of IP core usage, e.g....
Processors that deploy reconfigurable fabrics to implement application-specific accelerators on-demand obtained significant attention within the last decade. They trade-off the flexibility of general-purpose processors with the performance of application-specific circuits without tailoring the processor towards a specific application domain like application specific instruction set processors (ASIPs)...
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