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A 16-Mb DRAM chip fabricated in a 0.5- mu m CMOS process using silicided polysilicon, double metal, and trench storage is described. It incorporates an architecture that supports either 11/11 or 12/10 RAS/CAS (row-address strobe/column-address-strobe) addressing. It is segmented to utilize bit redundancy of 2 lines/137-b lines/half quadrant, and separate word-redundant array of 24 lines/quadrant,...
A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44- mu A current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe)...
An SRAM that has column-sliceable peripheral circuitry embedded in a 235 K CMOS gate array and improved flexibility in configuration is described. The port-configurable (PC) SRAM cell achieves the minimum area overhead associated with the configurability by using four port-customization terminals at every memory-cell boundary. Prior to customization, first and second polysilicon are used to connect...
A monolithic intelligent-power switch-mode integrated circuit designed specifically for use as a solenoid driver is described. It uses pulsewidth modulation (PWM) techniques to provide a pull-in current of 6 A and a hold-in current of 3 A. The device has internal control, self-protection, and diagnostic capabilities. It uses a bipolar IC process with an isolated vertical PNP transistor option. The...
A fully analog adaptive filter in BiCMOS technology, based on a given linear LMS (least-mean-square) adaption algorithm, is discussed. In the prototype filter the algorithm is realized using a combination of MOS switched-capacitor techniques and bipolar translinear cells for multiplications. Time sharing of op amps and multipliers saves area and power and is suitable for applications requiring a moderate...
A circuit that samples an image in two dimensions and uses a resistive network to average it spatially according to a Gaussian weighting function whose width is controlled by an electronically variable resistor is described. A matrix of logarithmic photoreceptors fabricated on the surface of the IC drives currents into the nodes of a mesh consisting of appropriately ratioed positive and negative resistors...
The image area of the frame FIT (frame-interline-transfer)-CCD (charge-coupled-device) image sensor is 14.0 mm (H)*7.9 mm (V), the effective number of pixels is 1920 (H)*1036 (V) and the unit cell size of a pixel is 7.3 mu m (H)*7.6 mu m (V). These specifications are for the high-definition-television (HDTV) format. The horizontal shift register consists of dual-channel, two-phase CCDs driven by a...
Basic design techniques and considerations for switched-current (SI) circuits are presented, and experimental results from integrated filters are given. By means of analogies to switched-capacitor circuits, a five-pole lowpass Chebyshev SI filter has been integrated in a 2- mu m N-well, double-metal CMOS technology. The average die area is about 200 mil/sup 2/ per SI pole. The current mirror gain...
A 320000-pixel self-scanned display with CMOS-TFT (thin-film-transistor) gray-scale generators is described. Integration of the scanning-circuitry needed to drive the 400*800-pixel active-matrix liquid-crystal display was achieved by fabricating both data-line and select-line driver circuits on the 127*228.6-mm rectangular glass substrate, along with the same polysilicon thin-film pixel transistors...
A 1- mu A-retention, 4-Mb SRAM with a thin-film-transistor (TFT) load cell, fabricated in a 0.5- mu m triple-poly-Si (first- and third-level W-polycide) double-Al CMOS technology is described. A 200-fA/b retention current is achieved. utilizing the PMOS-type TFT, in which the n/sup +/ diffusion area of the driver transistor acts as a gate electrode of the TFT. The RAM, which has a built-in voltage...
A CMOS LSI that integrates all analog-to-digital (A/D) and digital-to-analog (D/A) circuits, digital signal-processing circuits, and peripherals necessary for a digital NTSC (National Television System Committee) signal decoder on a single chip is described. The chip accepts composite NTSC signals in analog form, digitizes them, converts them to component RGB signals by digital signal processing,...
64 K*4 and 256 K*1 SRAMs with 8-ns access time and using a 1.0- mu m CMOS process are described. The circuits are designed with source-coupling techniques to achieve high-speed with small-signal swings, using only CMOS devices. A metal option permits selection of the 64 K*4 or 256 K*1 configuration. The same core architecture has also been used to generate *8 and *9 designs. One version achieves 3-ns...
A 20-ns, 4-Mb CMOS SRAM with both 4 M*1 and 1M*4 organizations and fabricated using a quadruple-polysilicon, double-metal, twin-well 0.6- mu m CMOS process technology is described. A word-decoding architecture and a sensitive sense amplifier, combined with an address transition detector (ATD) technique, realize high-speed, low-power operation. Because conventional divided-word-line (DWL) structure...
A 4-Mb (512 K*8) CMOS SRAM that uses a 0.5- mu m quadruple-poly double-metal CMOS technology to attain 23-ns address access time with a single 5-V external supply voltage and a load capacitance of 30 pF is described. Current-mirror/PMOS cross-coupled cascade sense amplifier circuits with a noise-immune data-latch circuit are used. A polysilicon PMOS load memory cell enables a 0.5- mu A standby current...
For the digital transmission of HDTV signals, special data-reduction techniques have to be used. One of these techniques is predictive coding or differential pulse-code modulation (DPCM). This coding technique removes redundancy from natural pictures without reducing spatial resolution. The critical timing path in these coders is defined by the recursive loop in the kernel. If the latency time of...
A 256K*16 graphic memory with a three-dimensional (3-D) bit map is discussed. The memory has on-the-fly selection of addressable data organized 16*1*1 or 4*4*1 in a 3-D bit map to support image processing. This access concept makes it possible to reduce the number of memory-fetch cycles to about one-sixteenth that of conventional RAMs. This is achieved by hierarchical decoding. The chip is fabricated...
A 10-A high-side driver device that has on-chip intelligence to provide self-protection and diagnostics for an automotive antilock braking system application is described. The device is fabricated by means of a multiepitaxial bipolar process that combines the ruggedness of discrete power transistors with junction-isolated IC circuits. The process combines single or multiple vertical epitaxial-base...
A decision circuit (DEC) that operates at speeds above 10 Gb/s and utilizes self-aligned AlGaAs/GaAs HBT (heterostructure-bipolar-transistor) technology is described. A DEC consists of a preamplifier, an internal buffer, a D-latch, and an output buffer. In a conventional DEC without an internal buffer, the output level of the high-gain amplifier does not match the logic level of the D-latch. This...
A fully differential charge redistribution analog-to-digital-converter (ADC) chip fabricated in a 5-V, 1.0- mu m CMOS process that includes polysilicide-to-metal capacitors, polysilicon resistors, and low-threshold n-channel transistors is discussed. The successive-approximation ADC uses self-calibration of capacitor, gain, and offset errors. Self-correction techniques are also used to eliminate first-order...
An 800-MHz digital-to-analog converter (DAC) that has a power dissipation of only 750 mW is described. The low power dissipation is achieved by the use of a decoder circuit and precise adjustment of timing and data multiplexing. This DAC, with on-chip video function capability, can be used for high-resolution displays of over 3000 lines or superfast waveform generators. A fast logic circuit utilizing...
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