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A fully integrated first-order wideband phase-locked loop (PLL), designed for hifi FM demodulation, is discussed. An SNR of 80 dB is obtained over an input frequency range from 5 to 8 MHz with a total harmonic distortion (THD) of -75 dB. The chip contains a high-gain limiter, a phase detector with a loop amplifier, a loop filter, and a low-noise oscillator. The power supply is 5 V, 13 mA, and a 1...
A self-regulating on-chip voltage-reduction circuit that adjusts the internal supply voltage to the lowest value compatible with chip speed requirements is described. Besides enhancing reliability, this technique allows power savings. The technique is based on regulation of the supply voltage of an equivalent critical path, a small circuit with delay V/sub dd/ properties proportional to those of the...
An analog/digital approach to data clock recovery that allows the implementation of a quasi-digital phase-locked loop (PLL) with an effective local clock frequency of 1 GHz in 2- mu m CMOS is described. The large phase jumps normally associated with digital PLLs are avoided. The basic concept of the clock recovery system is shown. A long ring oscillator (32 stages in this example) is permanently frequency...
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