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A fully differential charge redistribution analog-to-digital-converter (ADC) chip fabricated in a 5-V, 1.0- mu m CMOS process that includes polysilicide-to-metal capacitors, polysilicon resistors, and low-threshold n-channel transistors is discussed. The successive-approximation ADC uses self-calibration of capacitor, gain, and offset errors. Self-correction techniques are also used to eliminate first-order...
Oversampled delta-sigma converters have been used for high-resolution analog-to-digital conversion over a wide range of input frequencies. Oversampled converters reduce the need for complex antialias filters, eliminate sample-and-hold amplifiers, and are free of differential nonlinearity errors. A fourth-order converter with a dynamic range of 123 dB and a signal-to-total-harmonic-distortion ratio...
A self-calibrating, 18-b, serial-output, 100-ksample/s analog-to-digital converter (ADC) which is implemented on a 24-V BiCMOS analog chip and a 5-V, 2- mu m CMOS digital chip is described. This partitioning allows a larger input signal for better dynamic range, eases the comparator design, and protects analog circuitry from digital feedthrough. The two chips are wired in a 7.6-mm-wide, 16-pin plastic...
A two-step circuit in a fast bipolar technology that has higher sampling rate and analog bandwidth than previously reported monolithic 10-b analog-to-digital converters (ADCs) is discussed. A 75-MHz conversion rate with input bandwidth exceeding 100 MHz is achieved with 2-W power consumption.<<ETX>>
A fully differential CMOS videorate converter whose linearity relies on a binary-weighted capacitor array known to exhibit a 10-b linearity is described. The recycling analog-to-digital converter (ADC) does not have the sampling error found in other two-step or multistep pipelined architectures because it requires only one input sampling per conversion. A single-ended schematic of a digitally corrected...
A 10-b BiCMOS analog-to-digital converter (ADC) is used to demonstrate a current-mode pipeline system that overcomes some of the limitations of high-speed multiple-flash architectures. Although multistage ADCs are efficient in both die area and power, a track-and-hold amplifier (T/H) is required to prevent the input from changing while a conversion is taking place. If the ADC is pipelined (operating...
A videorate 10-b analog-to-digital converter (ADC), which is suitable for application in digital video cameras or high-definition TV (HDTV) and which has 6-b coarse and 5-b fine comparators is discussed. Four circuit techniques have been developed to realize 10-b resolution: (1) an overlapped interpolation method, (2) a differential folding circuit with a current switch and a current-mode analog bus...
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