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This paper deals with the ultra low-voltage design and application of an inverter-based driver. In order to ensure a reliable value of the overdrive voltage for transistors, the topology based on a boosting technique was used. The driver was designed in 130nm CMOS technology and verified by simulations including technology corners and measurement of prototyped chips. The whole boosted driver achieves...
This work deals with the influence of increasing rate of integration (i.e. technology downscale) on the main parameters of integrated circuits. Our concerns are focused on calibration methods of analog integrated circuits that can compensate undesired side effects of technology downscale. The paper describes both the general principle of calibration system as well as design requirements for main blocks...
This paper addresses a design and performance evaluation of a non-clocked comparator circuit intended to work in a wide temperature range with very low value of the power supply voltage. Due to low voltage swing, the input voltage range is set to be rail-to-rail. The target fabrication process is a standard twin-well 130 nm CMOS technology, with appropriate parameters required to meet circuit specifications...
This paper presents design of the inverter-based driver for low-voltage applications, with topology for boosting the transistors overdrive voltage. The proposed driver topology was designed through detailed circuit analysis and optimization, and it is suitable for use in a switched capacitor charge pump. The driver was designed in 130 nm CMOS technology and verified by simulations including technology...
The article addresses a design procedure of low-power variable gain amplifier employing so-called bulk-driven transistors in 130 nm CMOS technology, working with the power supply voltage of only 600 mV. Mentioned approach represents rather unconventional and still quite uncharted design technique. Therefore, the research potential is tremendous. The paper describes the proposed amplifier along with...
Different low-voltage and low-power techniques, which meets modern integrated circuit design requirements, appears as the key towards achievement of enhanced performance of designed circuits. For deep sub-micron technologies, choosing a suitable transistor model becomes very important. Conventional MOS transistor models, such as BSIM or PSP, are developed for conventional gate-driven applications...
The paper addresses the design of a bulk-driven variable gain amplifier (VGA) in 130 nm general purpose CMOS technology. The VGA is intended to be employed within a low-power automatic gain control (AGC) block, which requires an examination of possible gain setting approaches. The mentioned investigation as well as the evaluation and comparison of the obtained results are presented. The amplifier...
The paper deals with design and analysis of a variable-gain amplifier (VGA) working with a very low supply voltage, which is targeted for low-power applications. The proposed amplifier was designed using the bulk-driven approach, which is suitable for ultra-low voltage circuits. Since the power supply voltage is less than 0.6 V, there is no risk of latchup that is usually the main drawback of bulk-driven...
Design of variable-gain amplifier (VGA), based on fully differential operational amplifier is presented. The proposed VGA topology was verified through simulations and analysis of main circuit parameters. The VGA is designed in 0.35 μm CMOS technology using Cadence environment and BSIM3 family of models. Designed circuit works with the power supply of 3.3 V. The simulation results show that gain bandwidth...
In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-diven approach. As...
In this paper, different topologies of gate-driven and bulk-driven current mirrors designed in 90 nm CMOS technology are presented. Since the conventional MOS transistors can work as a bulk-driven device, there is no need for any modification of the existing MOSFET structure or technology process. The bulk-driven current mirror is capable of operating at power supplies down to the threshold voltage...
An alternative method of fault simulation is presented in this paper. The proposed method is based on impedance calculations in the circuit under test. Calculation time and other properties of the method are addressed and evaluated. Possible application and results evaluation are demonstrated on an experimental circuit. This method could improve the test development time and quality.
This paper presents the frontend part of the readout interface for a capacitive MEMS microphone designed and fabricated in 0.35 μm CMOS technology. The developed readout interface will be used in a noise dosimeter applicable in very noisy and harsh environment. The prototype chips were measured and the main parameters evaluated. The achieved results demonstrate low harmonic distortion, low noise and...
In this paper, a fully differential difference amplifier designed in 0.35 µm CMOS technology is presented. The proposed amplifier reaches high dynamic range and low input noise. Comparison of noise performance of the proposed fully differential difference amplifier to an ordinary differential amplifier has been performed. Simulation results prove that the developed amplifier circuit can be advantageously...
A fully differential difference amplifier designed in 0.35 µm standard CMOS technology is presented. The proposed topology reaches high dynamic range, low equivalent input noise and a low value of total harmonic distortion. Simulation results prove that the developed amplifier circuit can be advantageously used in high performance applications that require a fully differential signal processing.
The main goal of this paper is investigation of the fault coverage dependence on the value of the oscillation frequency in oscillation-based tests of analog circuits. For this purpose, an operational amplifier designed in 90 nm CMOS technology was used as a Circuit Under Test (CUT) in our experiment. Then, the CUT was transformed into an oscillator and different catastrophic faults were considered...
In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC) based on digitally compensated input offset of the operational amplifier (OPAMP) is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation...
A novel impedance fault simulations methodology is presented in this paper. This methodology is based on an equation that calculates two-point impedance using the eigenvalues and eigenvectors of the circuit's nodal admittance matrix. This approach is applicable to active and passive circuits in both DC and AC domains. Possible applications of the proposed methods in the design of integrated circuits...
This paper brings a detailed analysis and comparison of several charge pumps topologies that have not been optimized yet in order to make a relevant comparison of main parameters. The charge pumps were designed in a standard 90nm CMOS technology. A dedicated charge pump will be later used in an on-chip power management for energy-autonomous systems. In these applications, the maximum efficiency of...
A novel resistance calculation method based on eigen calculus of the circuit's nodal admittance matrix is described and evaluated in this paper. More specifically, the calculation time efficiency of the method is examined and comparison to the traditional LU factorization based method is made. This evaluation is based on real and complex matrices that are both symmetrical and non-symmetrical as well...
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