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In order to achieve 0.25 μm CMOS devices with industrial transfer capability, a 8" DUV lithography cell has been installed, including a 5500/90 ASM-L DUV stepper and a TEL Mark 8 track. An original physico-chemical screening test, based on DSC, allows us to select optimized DUV positive materials regarding to delay, environment and substrate sensitivity. Process optimization with selected materials...
Vertical nMOS transistors with channel lengths down to 70nm and thin gate oxides have been fabricated using LPCVD epitaxy for the definition of the channel region instead of fine line lithography. The devices show drain current and transconductance values comparable to very advanced planar transistors. For the shortest channel length a stronger increase of current is observed and is attributed to...
In this paper, the performance of a novel anode-shorted Lateral Insulated Gate Bipolar Transistor fabricated using a novel 500 V, 2.5 ??m digital HV-CMOS process is evaluated for the first time. The process sequence is unique in that it is common for all three technologies viz., the Junction Isolation, conventional Dielectric Isolation and the Double Epitaxial Layer Dielectric Isolation. Unlike the...
This paper reports an experimental study of a boron spike effect on electrical characteristics of SiGe HBTs fabricated by cold wall type ultra-high vacuum (UHV)/CVD technology. Two types of pre-treatment procedures were carried out to investigate the effect of the boron spike formed during heating step before epitaxial growth. One was Type-A (heating temperature=800??C) and the other was Type-B (HF...
The evolution of the active area/isolation transition has resulted in a modification of the isolation induced parasitic effects on the device. Using experimental results and simulations, we have analysed the corner parasitic transistor behaviour induced by an abrupt transition. We show that some technological parameters linked to the isolation process must be perfectly controlled for a good integration...
The impact ionization phenomenon in submicron LDD SOI MOSFETs is investigated using devices with body terminals. It is shown that in order to accurately model the impact ionization current for submicron LDD SOI MOSFETs, it is necessary to account for the voltage drop on the parasitic source-and-drain series resistances and for the gate-voltage dependent saturation field in the expression for the maximum...
The layout of bipolar power devices for e.g. (audio) amplifier applications has to be such that for a given chip-area the maximum amount of power can be dissipated. High dissipation can be a result of a large Vce, large Ic or a combination of both. It is known that thermal and electrical instabilities can occur in localised areas of the transistor, limiting the overall capabilities of the structure...
Results of an intensive study by means of XRD, SEM, AFM and TEM of the microstructure (i.e. the texture and morphology) of LPCVD silicon layers as a function of different process parameters are described. The influence of different deposition parameters, like partial and total pressure, doping, deposition and anneal temperature is shown. In particular the roughness of the silicon surface is investigated...
Single-step in-situ ultrathin (5-12 nm) Rapid Thermal Processing (RTP) silicon oxynitride dielectrics were fabricated on silicon and polysilicon planar and 3-D capacitor structures with sub-half micron dimensions. Physical and electrical characterization results show that these ultrathin dielectrics especially compatible for high density DRAM devices with 3-D stacked capacitors with sub-20 nm narrow...
The paper discusses mechanisms of process-induced damage observed in plasma etched CMOS devices. The low-level oxide leakage and degraded breakdown properties are investigated and experimentally simulated with thin oxide MOS structures. It is shown, that both low-level oxide leakage and degraded QBD, with their strong antenna dependence to plasma charging, are a result of temperature accelerated low-current...
Demand for temperature resistant semiconductor and circuit operation has reached significant levels in recent years. This paper describes the results of numerical simulation used to study the high temperature operation of heterojunction transistors incorporating wider band gap Gallium Nitride layers. Orders of magnitude reduction in drain an gate leakage current have been demonstrated over conventional...
In this paper we present the results of RF and noise measurements on MESFETs transplanted by epitaxial lift off (ELO). ELO is a technology by which epitaxially grown layers are lifted off from their growth substrate and are subsequently re-attached to a new host substrate. [1,2]. Gate leakage current as well as noise and RF characteristics of MESFETs and GaAs circuits are compared before and after...
We report on the investigation of the optoelectric properties of a Metal-Semiconductor-Metal (MSM) photodetector (PD) based on two-dimensional electron gas (2DEG). The layer sequence is compatible to an Al-free High Electron Mobility Transistor (HEMT) layer stucture in the InP/GaInAs material system [1]. Therefore our device can easily be integrated into HEMT circuits. The photoresponse of the MSM-2DEG...
We report on planar proton implanted vertical-cavity surface-emitting laser diodes (VCSELs) with high output powers and high wall plug efficiencies for top surface emission. For optimized mirror reflectivities and proper mode alignment with respect to the gain spectrum a maximum cw output power of 15.5 mW and power conversion efficencies of 17.6 % are achieved for not heat sinked devices.
The effects of dynamic self-heating in SOI MOSFETs are well known. For circuit simulation, it is attractive to model these effects using a simple first order electro-thermal model, but the validity of such models has not been verified previously. In this paper, direct measurements are presented of the small signal drain conductance of SOI MOSFETs for frequencies from DC up to 300 MHz. The conductance...
The purpose of this paper is to study the quantitative applicability of a laser-probe measurement system to conventional MOSFETs. Variations in the intensity and phase of the testing laser beam caused by the local changes in the refractive index of silicon due to variation in the free carrier concentrations are interferometrically detected and numerically modeled. The wave propagation through the...
An analytical investigation of the minority-carrier transport properties at arbitrary injection levels is presented. Firstly, it is shown that the minority-carrier transport equation is exactly soluble at high-injection levels, yielding closed-form expressions for the injected current, transit time and sheet resistance. Then, a simple analytical model valid at arbitrary injection levels is proposed...
Anomalous substrate current behavior at accelerated hot-carrier (HC) stress conditions is observed in LDD n-MOSFETs. HC stress is applied at maximum substrate current condition (VG??VD/2) on devices of a 0.7 ??m process with 15nm gate oxide thickness and effective gate lengths varying between 0.5 ??m and 1.2 ??m. Initially both drain and substrate current decrease during stress, due to hot-carrier...
Mixed-signal circuit design on sea-of-gates arrays requires the use of composite MOSTs, combinations of in-series and in-parallel connected unit MOSTs. To avoid an increase in circuit simulation complexity these are in general replaced by artificial single MOSTs. The analysis in this paper shows that a straightforward replacement will lead to incorrect results. Series MOSTs (in-series connected unit...
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