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This paper reports new results on programming performances and soft programming characteristics of scaled Flash memory cells fabricated with conventional and innovative p-pocket technologies. Soft-programming lifetimes of several devices are derived according to different procedures based on the effective temperature model of low voltage hot carriers (ETM). The results show that: a) these procedures,...
The large angle tilt implant technique has been used in two different manners to optimize MOS transistor performance. Large-Angle-Tilt-Implanted drain (LATIDs) were invented to improve n-channel transistor hot carrier immunity and the large angle implanted halos were used to suppress the subthreshold leakage. In this paper, we propose a new transistor architecture which applies a blanket LATID implant...
For many machine-vision and scientific applications, a high-resolution CCD imager with square pixels and operating in progressive-scan mode is required, because in many applications with fast moving scenes the time offset of image capture between the two interlaced fields of conventional broadcast-oriented imagers is unacceptable. The aim of this work was to modify the pixel of an existing interlaced...
A 10-mask 0.5-??m process is presented which combines three viable technology modules to achieve very small capacitances in a bipolar NPN transistor, whereas compatibility with mainstream CMOS is maintained. Shallow and deep trenches reduce the collector/base and collector/substrate capacitances by more than 50 %. Straps minimise dimensions of the active region by more than 50 %. Application of the...
A IV analog CMOS technology is developed as a subset of a 0.5μm n+/p+ dual poly gate CMOS process. In this process, "natural" threshold voltage MOSFETs are optimized to have a Vt of about 200mV set by well implants. Process architecture, SUPREM3 simulations, and some measured data are presented.
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