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We have successfully demonstrated a Vth controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the Vth controllability in terms of the size dependence such as the gate length...
The scaled FinFET flash memories with an oxidenitride-oxide (ONO) charge trapping (CT) layer have actively been developed in the past few years owing to the excellent short-channel effect (SCE) immunity of the FinFET [1, 2]. As a high-k dielectric blocking layer, an Al2O3 layer has also been used in the bulk FinFET flash memories [3]. Very recently, we have also developed floating-gate (FG) type SOI-FinFET...
The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field, was evaluated. The TFET was fabricated by inserting a parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit...
We report guidelines for symmetric threshold voltage (Vth) in double gate (DG) tunnel FinFETs (tFinFETs) with single and dual metal gate electrodes. To realize the symmetric Vth=±0.2V, the work function difference (ΔΦm) of each gate electrode in n- and p-type tFinFETs with a nondoped Si channel must be 1.34 eV, indicating that tuning the effective work functions in the dual metal gates is difficult...
Influence of work function (WF) uniformity of metal gates (MGs) on current-onset voltage (COV) fluctuation is investigated in detail for MG FinFETs. In addition to significantly suppressed variability of threshold voltage (Vt) itself, FinFETs with an amorphous TaSiN MG exhibit smaller COV fluctuation than that with a polycrystalline TiN MG. It is revealed that the COV variability is caused by the...
We analyzed the threshold voltage (Vth) shift due to EOT scaling in double gate (DG) tunnel FinFETs (tFinFETs). It is found that Vth in tFinFETs has high sensitivity of EOT, which is quite different as compared with MOSFETs. We proposed a simple model which is indispensable to design the tFinFETs structure for the first time. In order to correct the Vth modulation due to EOT scaling in tFinFETs, we...
A synthetic electric field effect to enhance the tunnel FET (TFET) performances is proposed. The TFET utilizes both orthogonal and parallel electric fields induced by a wrapped gate electrode configuration. The device concept was experimentally verified by fabricating Si-TFETs integrated with ultrathin epitaxial channel. Scaling of both the channel width and channel thickness enhances the TFET performance...
We demonstrate the monolithic integration of MOSFETs with thermo-optic (TO) Mach-Zehnder switches on SOI platforms. Successful driving operation was achieved for the TO switch via MOSFETs, which is promising for realizing driver-on-chip large-scale circuit switches.
Performance of a double-gate (DG) FinFET in the cryogenic environment is discussed based on measurements and simulation. It was found that the DG FinFET has an excellent immunity to the kink effect in the cryogenic environment. Our physics-based compact model reproduced the measured I–V characteristics. The successful demonstration of an opamp consisting of the DG FinFETs at 4.2 K is also presented.
CMOS tunnel FETs (TFETs) with vertical-tunnel-multiplication (VTM) were fabricated. VTM TFETs initiate band-to-band tunneling (BTBT) parallel to the gate electric field and effectively extend the tunnel area. Impact of the VTM was analyzed using a distributed-element circuit model, and the drain current multiplication by extended tunnel area was experimentally revealed for the first time.
It is well known that 3D channel devices, such as double-gate (DG) and tri-gate (TG) FinFETs, provide excellent short-channel effect (SCE) immunity. Thus, the scaled 3D channel FinFET flash memories with oxide-nitride-oxide (ONO) charge trapping layers have actively been developed [1–3]. Very recently, we have also developed floating-gate (FG) type SOI-FinFET flash memories [4–7]. In this paper, we...
For the first time, we have successfully fabricated the Vth controllable connected multigate FinFET on the world's thinnest 9-nm-thick extremely thin (ET) BOX SOI substrate. It was experimentally demonstrated that, by controlling the back (substrate) bias, the Vth of the FinFET on the ETBOX is flexibly tuned from low Vth to high Vth with keeping low sub-threshold slope.
The tri-gate (TG)- and double-gate (DG)-type poly-Si fin-channel split-gate flash memories with a thin n+-poly-Si floating-gate (FG) have successfully been fabricated, and their electrical characteristics including the variations of threshold voltage (Vt) and S-slope have been comparatively investigated. It was experimentally found that better short-channel effect (SCE) immunity, smaller Vt variations,...
The functional tri-gate flash memories with splitgate have been demonstrated for the first time, and its Vt variabilities before and after one P/E cycle have be systimetically compared with stack-gate ones. It was confirmed that split-gate shows smaller Vt distribution after erase and excellent over-erase immunity compared to those of stack-gate. Moreover, it was found that BVDS is higher than 3.2...
We experimentally investigated the device performance of n+- poly-Si/PVD-TiN stacked gate FinFETs with different Hfin's. It was found that mobility enhances in the tall Hfin devices due to the increased tensile stress. However, as Lg decreases, Ion for tall Hfin case becomes worse probably due to high Rsp. It was also confirmed that Vth variation increases with increasing Hfin due to the rough etcing...
The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel...
One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper...
Influence of NiSi S/D incorporation on parasitic resistance (Rpara) fluctuation of FinFETs was investigated in detail. While the NiSi S/D enhances the on current of the FinFET thanks to the Rpara reduction, it also causes additional Rpara fluctuation. Through analysis of correlation of Rpara with fin thickness and gate-to-NiSi offset fluctuation, it is revealed that NiSi/n+-Si contact resistance component...
As the scaling of conventional MOSFETs approaches its technological limit, the double-gate (DG) MOSFETs have emerged as an important candidate for the next generation device. As a novel device with an additional fourth terminal, the DG devices have a potential to evolve not only in the More-Moore way, i.e. short channel effects and variation prevention, but also in the More-than-Moore direction, i...
TR dependence of the electrical characteristics have systematically been investigated by fabricating PVD-TiN gate FinFETs. It was found that optimal TR is 915 °C for setting symmetrical Vth with a higher ION and the smallest σVth. It was also confirmed that carrier mobilities are independet of TR and comparable to those in the case of n+-poly-Si gate. The n+-poly-Si capping on PVD-TiN gate is very...
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