Krishna C. Saraswat

article

Analysis of Atomistic Dopant Variation and Fermi Level Depinning in Nanoscale Contacts

Gautam Shine, Krishna C. Saraswat

IEEE Transactions on Electron Devices > 2017 > 64 > 9 > 3768 - 3774

Using quantum transport simulations of metal–semiconductor junctions, we assess the viability of barrier thinning with dopants and barrier lowering with interfacial layers as solutions for contact resistivity in nanoscale transistors. Our atomistic simulations show that the discreteness of dopants leads to increasing variability in contact resistance as dimensions scale below 10 nm. We find that the...

article

Si Heterojunction Solar Cells: A Simulation Study of the Design Issues

Raisul Islam, Koosha Nassiri Nazif, Krishna C. Saraswat

IEEE Transactions on Electron Devices > 2016 > 63 > 12 > 4788 - 4795

Silicon heterojunction solar cells having semiconducting oxide-selective contacts can revolutionize the photovoltaic industry with the promise of low cost and high efficiency. In this paper, we have identified the potential design issues of silicon heterojunction cell using simulation. This paper compares two possible electron-selective oxides (TiO₂ and ZnO) and two possible hole-selective oxides...

article

Anomalous threshold reduction from <100> uniaxial strain for a low-threshold Ge laser

David S. Sukhdeo, Yeji Kim, Shashank Gupta, Krishna C. Saraswat, more

Optics Communications > 2016 > 379 > C > 32-35

We theoretically investigate the effect of <100> uniaxial strain on a Ge-on-Si laser. We predict a dramatic ~200x threshold reduction upon applying sufficient uniaxial tensile strain to Ge. This anomalous reduction is explained by how the topmost valence bands split and become anisotropic with uniaxial tensile strain. Approximately 3.2% uniaxial strain is required to achieve this anomalous threshold...

chapter

In-situ MOS gate engineering in a novel rapid thermal/plasma multiprocessing reactor

Mehrdad M. Moslehi, Man Wong, Krishna C. Saraswat, Steven C. Shatas

1987 Symposium on VLSI Technology > 21 - 22

1987 Symposium on VLSI Technology (SVLSIT)

Low temperatures and short times are essential requirements of future VLSI processing and the use of plasma in conjunction with single-wafer lamp heating is a major step to realize this goal, In-situ multiprocessing reduces contamination and enhances yield. Reproducible growth of thin oxides in hot-wall furnaces is difficult due to long transient times and constant furnace temperatures. Since furnaces...

article

Impact of minority carrier lifetime on the performance of strained germanium light sources

David S. Sukhdeo, Shashank Gupta, Krishna C. Saraswat, Birendra (Raj) Dutt, more

Optics Communications > 2016 > 364 > Complete > 233-237

We theoretically investigate the impact of the defect-limited carrier lifetime on the performance of germanium (Ge) light sources. For Ge LEDs, we show that improving the material quality can offer even greater enhancements than techniques such as tensile strain, the leading approach for enhancing Ge light emission. For Ge lasers, we show that the defect-limited lifetime becomes increasing important...

chapter

Properties and Trade-Offs of Compound Semiconductor MOSFETs

Tejas Krishnamohan, Donghyun Kim, Krishna C. Saraswat

Fundamentals of III-V Semiconductor MOSFETs > 7-27

In order to continue the scaling of silicon-based CMOS and maintain the historic progress in information processing and transmission, innovative device structures and new materials are required. A channel material with high mobility and therefore high injection velocity can increase ON current and reduce delay. Currently, strained-Si is the dominant technology for high performance MOSFETs. However,...

chapter

Study of Performances of Low-k Cu, CNTs, and Optical Interconnects

Kyung-Hoae Koo, Krishna C. Saraswat

Nanoelectronic Circuit Design > 377-407

Carbon Nanotubes (CNTs), Graphene Nanoribbons (GNRs), and Optical Interconnects and carbon nanotubes present promising options for replacing the existing Cu-based global/semiglobal and local wires. In this chapter, the performance of these novel interconnects is quantified and compared with Cu/low-κ wires for future high-performance integrated circuits. For a local wire, a CNT bundle exhibits a smaller...

chapter

Very High Performance, Sub-20nm, Strained Si and Si_x Ge_1-x, Hetero-structure, Center Channel (CC) NMOS and PMOS DGFETs

Tejas Krishnamohan, Christoph Jungemann, Krishna C. Saraswat

Simulation of Semiconductor Processes and Devices 2004 > 191-194

We present novel, very high performance, NMOS and PMOS strained-Si and SixGe_{(1_x)} heterostructure DGFETs suitable for scaling to sub-20nm dimensions. 1-D Poisson-Schrodinger simulations show that the devices exhibit Center-Channel (CC) operation. Full-Band Monte Carlo simulations show a ~50% increase in drive currents and ~2X increase in switching speeds at lower capacitance compared to conventional...

chapter

Analytical Modeling of Ge and Si Double-Gate(DG) NFETs and the Effect of Process Induced Variations (PIV) on Device Performance

Abhijit Pethe, Tejas Krishnamohan, Ken Uchida, Krishna C. Saraswat

Simulation of Semiconductor Processes and Devices 2004 > 359-362

In this paper, we present a self-consistent, analytical model that includes carrier quantization; short channel effects (SCE) and calculates the ballistic currents in DGFETs. We use this new tool to compare the effect of SCE and process induced variations (PIV) on Silicon (Si) and Germanium (Ge) NMOS DGFETs. Our results show that in the case of DGFETs designed to meet the ITRS High Performance (HP)...

chapter

Thermal modeling of metal oxides for highly scaled nanoscale RRAM

Sanchit Deshmukh, Raisul Islam, Clare Chen, Eilam Yalon, more

2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) > 281 - 284

2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

Resistive random access memory (RRAM) is a promising candidate for future non-volatile memory applications due to its potential for performance, scalability and compatibility with CMOS processing. The switching in the RRAM cell occurs via formation of conductive filaments composed of sub-stoichiometric oxide (SSO). In this work, we model thermal conduction in a pair of neighboring memory cells, taking...

chapter

Strained Ge nanowire with high-Q optical cavity for Ge laser applications

Donguk Nam, Jan Petykiewicz, David S. Sukhdeo, Shashank Gupta, more

2015 IEEE 12th International Conference on Group IV Photonics (GFP) > 135 - 136

2015 IEEE 12th International Conference on Group IV Photonics (GFP)

We present a novel structure that simultaneously achieves high tensile strain, pseudo-heterostructure, and high-Q optical cavity in a pure Ge layer. Employing our structure in a GeSn layer will enable a truly practical Si-compatible laser.

article

Surface Passivation of Germanium Using SF₆ Plasma to Reduce Source/Drain Contact Resistance in Germanium n-FET

Gwang-Sik Kim, Seung-Hwan Kim, Jeong-Kyu Kim, Changhwan Shin, more

IEEE Electron Device Letters > 2015 > 36 > 8 > 745 - 747

We demonstrate Fermi-level unpinning and contact resistance reduction by surface passivation using SF₆ plasma treatment of a metal/germanium (Ge) contact. A specific contact resistivity (

$\rho _{\mathbf {c}})$

of 1.14

$\times 10^{\mathrm {\mathbf {-3}}}~\Omega \cdot $

cm

$^{\mathrm {\mathbf {2}}}$

and 0.31 eV of Schottky barrier height is achieved for a Ti/SF₆-treated n-type Ge (n-Ge) (

$N_{\mathbf {d}}=$

...

chapter

Nickel oxide carrier selective contacts for silicon solar cells

Raisul Islam, Pranav Ramesh, Ju Hyung Nam, Krishna C. Saraswat

2015 IEEE 42nd Photovoltaic Specialist Conference (PVSC) > 1 - 4

2015 IEEE 42nd Photovoltaic Specialists Conference (PVSC)

Highly selective contacts which allow one type of carrier (e.g. holes) to conduct and block the other type (e.g. electrons) are the key to achieving high efficiency in thin-film solar cells. Metal-insulator-semiconductor (MIS) carrier selective contacts can make a solar cell possible without a diffused p-n junction. In this work, we introduce nickel oxide (NiO) as a potential hole selective (electron...

article

Reduction of Surface Roughness in Epitaxially Grown Germanium by Controlled Thermal Oxidation

Woo-Shik Jung, Ju Hyung Nam, Ashish Pal, Jae Hyung Lee, more

IEEE Electron Device Letters > 2015 > 36 > 4 > 297 - 299

Obtaining a smooth substrate with surface roughness of 2 Å is essential for semiconductor device fabrication. In this letter, we characterize the effect of thermal oxidation of epitaxially grown Ge on its surface roughness. First, the effect of oxidation on root-mean-square roughness is investigated for epi-Ge surface that is bombarded with phosphorous ions. Next, the effect of oxidation is investigated...

chapter

Extended Hückel theory for quantum transport in magnetic tunnel junctions

Gautam Shine, Sasikanth Manipatruni, Anurag Chaudhry, Krishna C. Saraswat, more

2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) > 301 - 304

2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

Spin-resolved conductivities in magnetic tunnel junctions are calculated using a semiempirical tight-binding model and non-equilibrium Green's functions. The performance of half-metallic electrodes is studied by comparing conventional Fe-MgO-Fe structures to Co₂FeAl-MgO-Co₂FeAl structures. The results show higher tunneling magnetoresistance and resistance-area product for Co₂FeAl devices across a...

chapter

Metal/insulator/semiconductor carrier selective contacts for photovoltaic cells

Raisul Islam, Krishna C. Saraswat

2014 IEEE 40th Photovoltaic Specialist Conference (PVSC) > 285 - 289

2014 IEEE 40th Photovoltaic Specialists Conference (PVSC)

A novel solar cell structure using metal/insulator (TiO₂ and NiO)/semiconductor (MIS) structures as carrier selective contacts on both Si and GaAs is proposed. These cells do not use any diffused p-n junction to separate the carriers. Simulations show that these cells can provide a very high open circuit voltage. Using MIS contacts a three terminal multi-material solar cell composed of two independently...

chapter

How far can we push Si CMOS and what are the alternatives for future ULSI

Krishna C. Saraswat

72nd Device Research Conference > 3 - 4

2014 72nd Annual Device Research Conference (DRC)

Si CMOS technology has dominated the microelectronics industry, with continued scaling. However, future Si CMOS scaling is reaching practical and fundamental limits. Diminishing improvement in the on current and increase in off current are beginning to limit the scaling of bulk Si CMOS. Currently, strained-Si channel with high-k dielectric and metal gate is the dominant technology for high performance...

chapter

Improving contact resistance in MoS₂ field effect transistors

Chris D. English, Gautam Shine, Vincent E. Dorgan, Krishna C. Saraswat, more

72nd Device Research Conference > 193 - 194

2014 72nd Annual Device Research Conference (DRC)

MoS2 is a material of interest for two-dimensional (2D) field effect transistors (FETs) [1-3], however contact resistance (R_c) remains a key limiting factor. Here we present a systematic study of contact resistance to MoS2 using various metals with different deposition conditions, compared to detailed simulations. We find that decreasing the metal deposition pressure improves the metal-MoS2 interface...

article

Study of Carrier Statistics in Uniaxially Strained Ge for a Low-Threshold Ge Laser

Donguk Nam, David S. Sukhdeo, Shashank Gupta, Ju-Hyung Kang, more

IEEE Journal of Selected Topics in Quantum Electronics > 2014 > 20 > 4 > 1 - 7

In this paper, we present a comprehensive study of carrier statistics in germanium with high uniaxial strain along the [1 0 0] direction. Several types of PL experiments were conducted to investigate polarization-, temperature- and excitation-dependent carrier statistics in germanium under various amounts of uniaxial strain. With the ability to clearly resolve multiple photoluminescence peaks originating...

article

The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances

Jeong-Kyu Kim, Gwang-Sik Kim, Hyohyun Nam, Changhwan Shin, more

IEEE Electron Device Letters > 2014 > 35 > 12 > 1185 - 1187

We investigate the impact of metal-interfacial layer-semiconductor source/drain (M-I-S S/D) structure with heavily doped n-type interfacial layer (n⁺-IL) or with undoped IL on sub-10-nm n-type germanium (Ge) FinFET device performance using 3-D TCAD simulations. Compared to the metal-semiconductor S/D structure, the M-I-S S/D structures provide much lower contact resistivity. Especially, the M-I-S...

INFONA - science communication portal

Search results for: Krishna C. Saraswat

Analysis of Atomistic Dopant Variation and Fermi Level Depinning in Nanoscale Contacts

Si Heterojunction Solar Cells: A Simulation Study of the Design Issues

Anomalous threshold reduction from <100> uniaxial strain for a low-threshold Ge laser

In-situ MOS gate engineering in a novel rapid thermal/plasma multiprocessing reactor

Impact of minority carrier lifetime on the performance of strained germanium light sources

Properties and Trade-Offs of Compound Semiconductor MOSFETs

Study of Performances of Low-k Cu, CNTs, and Optical Interconnects

Very High Performance, Sub-20nm, Strained Si and Si_x Ge_1-x, Hetero-structure, Center Channel (CC) NMOS and PMOS DGFETs

Analytical Modeling of Ge and Si Double-Gate(DG) NFETs and the Effect of Process Induced Variations (PIV) on Device Performance

Thermal modeling of metal oxides for highly scaled nanoscale RRAM

Strained Ge nanowire with high-Q optical cavity for Ge laser applications

Surface Passivation of Germanium Using SF₆ Plasma to Reduce Source/Drain Contact Resistance in Germanium n-FET

Nickel oxide carrier selective contacts for silicon solar cells

Reduction of Surface Roughness in Epitaxially Grown Germanium by Controlled Thermal Oxidation

Extended Hückel theory for quantum transport in magnetic tunnel junctions

Metal/insulator/semiconductor carrier selective contacts for photovoltaic cells

How far can we push Si CMOS and what are the alternatives for future ULSI

Improving contact resistance in MoS₂ field effect transistors

Study of Carrier Statistics in Uniaxially Strained Ge for a Low-Threshold Ge Laser

The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances

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