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Fine-pitch inter-strata connections in 3-D stacking lack rework solutions which can aide in early learning for 3-D integration. Reduced solder volume in the microbump or micropillar is also less tolerant to non-planarity and non-uniformity of the strata and interconnection array, especially as die size and number of interconnections increase. At fine pitch, heavily-loaded thermal underfills can have...
In this work, thinned Si chips were stacked using conventional C4 (controlled collapse chip connection) technology. The test chips consisted of CMOS-compatible thru-silicon via (TSV) interconnects at a pitch of 200 mum and integrated deep trench (DT) capacitors. The DC resistance of a TSV and a C4 bump is measured to be less than 10 mOmega and capacitance density of 14 muF/cm2 and 28 muF/cm2 were...
A robust through-silicon via technology is necessary for high-power, high-performance 3D-silicon applications. To study through-via interconnection reliability, modules consisting of a test chip, silicon carrier interposer with through-vias, and ceramic substrate were constructed. A socket assembly containing a microchannel water cooler was also constructed to apply pulsed power to via daisy chain...
We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-mum thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding...
Three-dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration options can leverage stacked die and/or silicon packages depending on applications. The enabling technology elements include: (i) through-silicon-vias (TSV) with thinned silicon wafers, (ii) fine pitch wiring, (iii) fine pitch interconnection between...
In this paper a three-dimensional (3D) chip stacking technology using fine-pitched interconnects with lead-free solder is described. Different interconnect metallurgies such as Cu/Ni/In, Cu/In and Cu/Sn were considered and the bonding conditions to optimize the bonding parameters were determined. The effect of intermetallic compound (IMC) formation on the mechanical properties of the joins is discussed...
System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing...
A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance electronic systems. Newly developed technology elements include: electrical silicon through-vias, fine-pitch, high bandwidth wiring, fine pitch solder interconnection, fine pitch known-good-die, and advanced microchannel cooling. Applications may...
In the past, traditional CMOS scaling has been one of the principal levers to achieve increased system-level performance. Today, scaling is becoming increasingly difficult and less effective, and a range of new two- and three-dimensional silicon integration technologies are needed to support next-generation systems. A silicon-carrier system-on-package (SOP) is an advanced packaging solution, enabling...
To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder micro-joints (fine pitch flip-chip interconnections) for our system-on-package (SOP) technology. We fabricate solder bumps with 25 mum (or less) in diameter on 50 mum pitch size, as...
This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable,...
Heterostructure design and device fabrication techniques in GaAs/AlGaAs for vertically integrated p- and n-channel quantum-well FETs are described, and the operation of FETs fabricated on a p/n double-quantum-well heterostructure is demonstrated. The dependence of parasitic resistance and gate leakage on heterostructure layer parameters and device geometry is examined in experiments. Contact and n/sup...
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