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The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary...
Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits...
Reliability of charge trapping (CT) devices has been examined in detail, and the path to sub-30nm NAND flash is investigated. All CT devices are vulnerable to edge effects (non-uniform injection and non-uniform Vt along the device width). This degrades both the endurance and the ISPP programming efficiency, but the effect can be minimized by careful engineering. Metal gate and high-K dielectric can...
The interference and fringing field effects beyond sub-30 nm node charge-trapping(CT) NAND Flash are studied critically using 3D simulation. Due to the relatively large EOT (>15 nm) compared to the device dimension (F), the most severe interference comes from adjacent pass-gate WL bias disturb through the edge fringing field effect. On the other hand, the program charges in adjacent devices generate...
Barrier engineered charge-trapping NAND flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multi-layer barrier is derived using WKB approximation. The rigorously derived analytical form is valid for both electron and hole tunneling, as well as for any barrier composition. With this, the time evolution...
In NAND flash, devices are normally erased to negative Vt and then programmed to positive Vt. In this work we introduce a novel depletion-mode (normally on) buried-channel, junction-free n-channel NAND flash device. The buried-channel NAND flash shifts the P/E Vt ranges below those for the conventional surface-channel device, and is more suitable for the NAND Flash memory design. Due to the lower...
This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in...
We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field...
Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight VT distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND Flash are studied extensively in this work. Experimentally we find that the ISPP slope is very close to 1 for BE-SONOS capacitors for a wide range of EOT and O1 variations. A theoretical model is developed to prove that ISPP slope~1 is a universal...
A high-performance body tied FinFET BE-SONOS device is demonstrated, suitable for NAND Flash memory scaling beyond 30 nm technology node. BE-SONOS offers efficient hole tunneling erase and excellent data retention. When integrated into a FinFET structure, a much higher program/erase speed is obtained, owing to the inherent field enhancement (FE) effect around the fin tip. In this work, a very scaled...
For the first time, a successful TFT NAND-type flash memory is demonstrated using a low thermal budget process suitable for stacking the memories. A TFT-SONOS device using bandgap engineered SONOS (BE-SONOS) (Lue, et al. 2005) with fully-depleted (FD) poly silicon (50 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.18/0.09 mum) with good DC performance are...
A novel p-channel NAND-type non-volatile flash memory using nitride-trapping device is presented. The p-channel device is programmed by very efficient band-to-band tunneling hot electron (BBHE), and erased by self-converging channel hole tunneling. An ultra-thin bandgap engineered ONO tunneling dielectric as presented in H. T. Lue et al. (2005) is adopted to achieve efficient hole-tunneling erase...
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