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Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits...
Reliability of charge trapping (CT) devices has been examined in detail, and the path to sub-30nm NAND flash is investigated. All CT devices are vulnerable to edge effects (non-uniform injection and non-uniform Vt along the device width). This degrades both the endurance and the ISPP programming efficiency, but the effect can be minimized by careful engineering. Metal gate and high-K dielectric can...
The interference and fringing field effects beyond sub-30 nm node charge-trapping(CT) NAND Flash are studied critically using 3D simulation. Due to the relatively large EOT (>15 nm) compared to the device dimension (F), the most severe interference comes from adjacent pass-gate WL bias disturb through the edge fringing field effect. On the other hand, the program charges in adjacent devices generate...
Barrier engineered charge-trapping NAND flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multi-layer barrier is derived using WKB approximation. The rigorously derived analytical form is valid for both electron and hole tunneling, as well as for any barrier composition. With this, the time evolution...
In NAND flash, devices are normally erased to negative Vt and then programmed to positive Vt. In this work we introduce a novel depletion-mode (normally on) buried-channel, junction-free n-channel NAND flash device. The buried-channel NAND flash shifts the P/E Vt ranges below those for the conventional surface-channel device, and is more suitable for the NAND Flash memory design. Due to the lower...
This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in...
We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field...
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