The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Delay test is crucial for finding slow paths and slow ICs, both during bringup and during speed binning. Path delay test has traditionally been considered to be superior in finding slow paths. This paper describes our experiments indicating that this is not always the case. For the UltraSPARC T2 microprocessor series we found that transition delay test often ran slower, was more effective in finding...
The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip...
Higher coefficient of thermal expansion (CTE) of printed wiring board (PWB), compared with that of silicon chip, makes the impact on thermally induced stress in IC chip by PWB a great concern for IC with Low-K inter-metal-dielectric (IMD) product reliability. To characterize and validate the 65 nm technology flip-chip (FC) package reliability, 20times20 mm2 test chip were assembled in a 42.5times42...
In this paper, a new phenomenon regarding to failure bit count (FBC) distribution and data retention time of embedded DRAM with high-K dielectric Ta2O5 MIM capacitors has been observed and explored. Different from conventional knowledge with FBC increase or retention time reduction of DRAM after burn-in, it is found FBC decreased and retention time increased in the sub-0.1mum embedded DRAM technology...
Wafer-level ramped voltage to dielectric breakdown testing (RVDB) on copper/low k interconnect dielectrics has been used for reliability assessment and is motivated by practical needs for shortened test cycle time and large sampling for accurate statistical characterization. This work has identified a meaningful correlation between RVDB and TDDB (time dependent dielectric breakdown), which demonstrates...
The read disturb failure mechanism reported causes unselected erased bits residing on selected wordlines to gain charge under low field conditions, causing them to appear programmed. This failure appears to be due to electron tunneling barrier lowering by positive charge trapped during program/erase cycling. The Si-SiO/sub 2/ barrier in failing bits is reduced from 3.0 eV to under 1.0 eV at 70 degrees...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.