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Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCut™ technology which already allows achieving a maximum total SOI layer thickness variation of less than ± 10 Å on preproduction volume. Total thickness variation of ± 5 Å is targeted.
The current status of SOI technology using wafer bonding is reviewed and its technological positioning in CMOS scaling is discussed. While bulk CMOS technology is encountering various kinds of critical issues, SOI technology using wafer bonding provides unique solutions by virtue of its flexible material design. Mobility enhancement through strained-SOI (sSOI) or optimization of crystal orientation...
Ultra-scaled Z-RAM cells based on MuGFETs are demonstrated for the first time. Effects of physical parameters such as channel doping concentration, fin width, and gate length on Z-RAM cell performance are discussed. Transient measurements and simulations prove that the basic operational principles are effective on Z-RAM cells with a gate length down to 12.5 nm.
To meet HP and LP circuit requirements, increasing channel mobility is required to boost transistor performance and/or reduce Vdd for lower power dissipation without performance penalty. The ultra-thin body (UTB) devices with undoped and strained channels can be used to control the SCE and reduce the sub-threshold leakage for scaling and low power dissipation. Implementing strained-silicon is not...
In this paper, 300 mm high resistivity (HR) SOI UNIBONDtrade material is evaluated using RF component and millimeter wave (MMW) function realized in advanced 65 nm HR SOI CMOS technology. The goal is to investigate the insulating behavior, in term of resistivity homogeneity all over the wafer, of 300 mm wafer provided by SOITEC and to offer a benchmarking with well known 200 mm material. For this...
This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride capping layer, and embedded SiGe source/drain. Through novel strain engineering, nFET/pFET Idsat enhancements as high as 27%/36% have been achieved for sub-40nm devices at 1V with 30% reduction in gate leakage current, while introducing minimum...
Substrate amorphization prior to Source/Drain implantation is used for shallow junction fabrication. The impact of preamorphization on CMOS Performance is investigated. Results for a 1.5??m double well CMOS Technology with phosphorus and boron drains are presented. The influence of preamorphization on the transistor characteristics, speed and latch-up hardness is discussed.
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