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We developed a 4Mb split-gate e-flash on 28-nm low-power HKMG logic process, which demonstrates the smallest bit-cell size (0.03×-um2) for high performance IoT applications. High speed operation (25us write time and 2ms erase operation) and robust reliability (500K cycle, 10 years retention) are achieved through optimization of triple-gate flash architecture and scaling of word-line (WL) transistor...
We present a highly scalable 2nd generation 45-nm split-gate embedded flash, which has been scaled of 40% unit-cell-size (almost same size with 28-nm technology node) from the 1st generation 45-nm embedded flash without using extra masks, processes and advanced-equipment. By optimizing process of triple-gate flash architecture and implementing several design methodologies, high speed operation (10ns...
For the first time, 4Mb split-gate type embedded flash is developed in 45-nm technology with 1M cycling endurance for mass production of various applications. Process integration is designed for logic compatibility, minimizing shift of logic device characteristics so that existing IPs can be used. By process optimization of triple-gate flash architecture, high speed operation (write time of 25us and...
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