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A reconfigurable heterogeneous 3D-IC is assembled from two 28 nm FPGA die with 580 k logic cells and two 65 nm mixed signal die on a 65 nm interposer in a 35 mm 2 CS-BGA package. One mixed signal die consists of sixteen 16 bit current steering DACs, the other die consists of sixteen 13 bit pipelined ADCs. The interposer provides optimal system partitioning; noise isolation and high density interconnect...
Data converters are required to interface digital processing engines, for example FPGAs, to the real world. Data conversion is typically accomplished using discrete devices that are interfaced to the FPGA using various IO standards. However, exponential growth in bandwidth as a result of increasing channel count and higher sample rate means this IO interface is becoming a limiting factor in the system...
This paper presents a realised prototype of fully integrated CMOS LC-PLL frequency synthesizer. The circuit delivers a wide range of clock signals between 12 MHz and 5800 MHz, with average long term jitter of only 4 ps. The primary application of the presented circuit includes high speed series data transmission links. Low power consumption of the complete synthesizer (including bias circuitry), in...
In this paper we present the design of a low power VCO with reduced variations in VCO gain (KVCO) and sub-band spacing resolution (fres). The proposed VCO is designed using a 90nm CMOS process to cover a tuning range of 23%. Variations in KVCO and fres are reduced by factors of 6 and 17 respectively over a conventional sub-banded VCO, designed using the same process, to meet the same tuning range...
This paper presents a novel technique to achieve fast calibration of the voltage-controlled oscillator (VCO) into the optimum subband of operation. The proposed technique is pre-dominantly digital thus exhibiting low power/area requirements, in addition to greatly reduced calibration times, suitable for application in lower technology nodes. To verify the proposed technique the VCO and corresponding...
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