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In this study, the influence of sidewall thickness on the threshold voltage and on-current of L-shaped Impact-ionization metal-oxide-semiconductor transistor (I-MOS) is investigated. For the sidewall thickness in the range of 10 nm to 20 nm, the devices of thicker sidewall show lower on-current and higher threshold voltage. This is because the electron concentration between the channel and the most...
In this paper, we introduce a buried-gate fin and recess channel MOSFET (BG-FiReFET) for a high performance and low power application. The source/drain region in the BG-FiReFET becomes wider than that of the conventional FinFETs without the epi-process. It can alleviate the burden of the high parasitic resistance. We have adopted a buried-gate structure to avoid GIDL current, which has non-overlapped...
A capacitor-less one-transistor DRAM cell with surrounding gate MOSFET with vertical channel (SGVC) using gate-induced drain leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact ionization current, the write operation with GIDL current provides high sensing margin owing to higher potential barrier between body and source. To confirm...
In this paper, we present a novel fin and recess channel MOSFET (FiReFET) which has low leakage current as well as excellent current drivability. In contrast to the bulk-FinFET, the FiReFET has trench gates which can lead to the reduction of the off-state leakage current without the punch-through stop implantation. Furthermore, it is possible to enhance the on-state current against the RCAT using...
A novel asymmetric MOSFET with no lightly doped drain on the source side is simulated on bulk Si using a device simulator (SILVACO). To overcome the problems of the conventional asymmetric process, a novel asymmetric MOSFET using a mesa structure and a sidewall spacer gate is proposed, and it provides a self-alignment process, aggressive scaling, and better uniformity. First of all, we have compared...
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