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Nanotwinned copper (nt-Cu) is drawing wide attention for it simultaneously demonstrates high strength and high ductility, which are thought to be mutually exclusive. According to previous studies, nanotwinned Cu may be the best structure for resisting electromigration damage. In this study, we deposit (111)-oriented nt-Cu using direct current with suitable additives on PCB substrates. Current density...
This paper is to present an assembly structure of system-in-package (SiP) module using the glass substrate with through-glass via (TGV) where the diameter of TGV is 100μm and the glass substrate is 200μm thick. The glass-substrate is first laminated with a dielectric material on the surface and in through vias; then drill through holes in the dielectric material inside the vias, respectively. The...
The requirement of IC packages with fine line features has increased significantly. Semi-Additive Process (SAP) is the traditional way to make copper trace in the organic substrate. However, inadequate adhesion of fine line to dielectric materials occurred in manufacturing for line/space less than 5/5µm. Line embedded (LE) is another way to form fine circuitry. LE technology has several advantages...
As society goes to mobile, data bandwidth is required to increase every year. Memory industry community is responsible for products like DDR3, DD4 and for mobile LPDDR3 and LPDDR4, etc. However, the products launching speed do not match well with the industry requirements. Hence revolutionary specs, such as HBM, HMC, and wide I/O 1 and wide I/O 2 have been proposed. However, to realize these memory...
Interposer technology has been developed for providing a fine line/space and high density interconnections that cannot be matched by current laminate substrate technology. Interposer materials such as silicon, glass and organic had been under intensive development. We have been developing EIC (Embedded Interposer Carrier) technology which eliminates the interconnection between the interposer and the...
For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, managing the substrate warpage along processing steps becomes critical. Thin organic substrates face challenging warpage issues in manufacture and in chip assembly. Glass is one of the candidates that can be used in substrate to replace traditional organic substrate...
The increasing demand of advanced electronics devices with ever increasing of functionality and performance have driven semiconductor industry to scale down in feature size of the Integrated Circuits. The semiconductor industry still follows the Moore's Law.
For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, fine line substrate technology becomes critical. Current organic substrates are limited to line/space larger than 8/8 µm for by conventional semi-additive plating (SAP) technology. It may have yield loss issue due to weak adhesion of line/space less than 5/5 µm,...
Current organic substrates are limited to lines/space 10/10 μm and via size around 50 μm. However, the semiconductor with advance node needs fine line/space of 5/5 or 3/3 and even 2/2 μm in the future. Interposer provides a high density interconnection with fine line and small via that cannot be matched by current laminate substrate technology. We have proposed a new structure that embedded interposer...
The rapid growth of smartphones and tablets in mobile market demands the packaging technology to be in a thinner profile with small form factor and reduce power consumption. The PoP structure is widely used in the package of smart phones to connect memory and Application Processor. Even if TSV is the preferred structure for connecting memory and AP, the high cost of TSV process prohibit TSV for wide...
PoP structure is widely used in mobile devices which memory package is directly attached to the top of the application processor. This structure, which has a smaller form factor and short interconnection distance between memory and processor chip. As the market demands more speed and bandwidth, the memory devices are moving from LPDDR to LPDDR3 and even wide I/O to support future requirements. Since...
It is well known that 3DIC integration is the next generation semiconductor technology with the advantages of small form factor, high performance and low power consumption. However the device TSV process and design rules are not mature. Assembly the chips on top of the Si interposer is the current most desirable method to achieve the requirement of good performance. In this study, a new packaging...
Existing popular temporary bonding techniques for TSV thin wafer handling can be classified into three categories: (1) Carrier with via hole structure, for example: solution provided by TOK (zero Newton) process (2) Adhesion Layer separation type, for example: solution provided by 3M (WSS) process (3) High temperatures debonding process, solution for example: provided by Brewer Science (HT) process...
In this study, a flexible wafer level packaging (FWLP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the FWLP, the diced chip is picked and back-sided attached to the flexible substrate after the functional testing. Besides, the solder on rubber (SOR) design is applied to expand...
The robustness and dimensions of metal trace is important for electronic packaging applications. For example, materials with good electrical conductivity are essential for reducing IR drops for integrity of electrical signals. Copper metal has good electrical conductivity and hence is the major materials used in electronic packaging. For example in PCB industry, the common methods to form copper trace...
SiP technology has been one of the alternative solutions to system integration. Compare to SoC, SiP has the advantages of integration of dies made from different technologies, e.g. GaAs and Silicon. In some cases, SiP technology may provide faster time to the market and at a lower cost. Despite many research activities, there are few companies actually went into mass production using SiP embedded...
In this study, the modified panel base package (PBP) technology with enhanced cover layer is proposed to improve packaging reliability. One cover layer which has larger Young's modulus than the lamination material is applied to restrain the expansion/shrinkage of dielectric. The testing samples are fabricated and tested under temperature cycling. Besides, three-dimensional finite element (FE) analysis...
A new panel base package (PBP) technology that was developed based on the concepts of the wafer level package (WLP) has been proposed in order to obtain the signal fan-out capability for the fine-pitched integrated circuit (IC). In the PBP, the chip is attached to a selected chip carrier, and the volume of IC devices is extended for the redistribution of the original die pads. In this study, the thermal...
The wafer level package (WLP) is a cost-effective solution for the electronic package, and has been increasingly applied during recent years. In this study, a new packaging technology developed based on the concepts of the WLP, the panel base package (PBP) technology, is proposed in order to further obtain the capability of signals fan-out for the fine-pitched integrated circuit (IC). In the PBP,...
In this research, the objective is to develop a stress-buffer-enhanced package subjected to board level drop test under a high-G impact drop; both drop test experiments and ANSYS/LS-DYNA simulations are executed. Many researchers indicate that solder joints in wafer level chip scale package (WLCSP) are the weakest portion in board-level drop test because of the large relative motion between the board...
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