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We measured RTN characteristics in NAND flash cell array and test structure having 27 nm design rule depending on different program and erase states. From these measured results, we analyzed the trap properties along the active width direction from of NAND flash cell. Using special analysis methods, we verified the validity of this characterization tool and applied it to various processed NAND flash...
We have investigated a new program disturb phenomenon by DIBL (drain-induced barrier lowering) in MLC NAND Flash device. It is found that lower programmed state cell shows large DIBL effect and its BVdss measurement results in unwanted programming of nearby erased state cells. It is attributed to punch-through leakage of programmed state cell during BVdss measurement. Electrons from this leakage are...
A new self-boosting phenomenon is observed in 51 nm NAND flash devices. The authors have modeled and named this observation 'local self-boosting by source/drain depletion cutoff, a result of low net N-type dopant in the source/drain region. As cell-to-cell design rules shrink into the 50-nm range, channel dopant is increased to reduce short-channel effects while implantation-related source/drain dopant...
One of the most important performances of NAND flash memory is reliability characteristics, such as program/erase cycling and data retention. Tunnel oxide quality is essential to the reliability and it is well known that tunnel oxide degradation during FN (Fowler-Nordheim) stress is due to the oxide trap and interface trap generation. It is believed that trapping mainly occurs where tunnel oxide is...
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