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We have developed a reliable and predictable TCAD modeling method for retention characteristics of the charge trap NAND Flash device. This modeling method can explain various retention phenomena related to temperature, program pattern, and bake time. The temperature dependency is well described by direct tunneling and thermionic emission, the pattern dependency can be explained by carrier diffusion...
We have investigated a mechanism for an abnormally large floating gate (FG) interference reported in 2y nm NAND flash device. Based on the experimental and simulation results, we have found that the root cause is attributed to a depletion of polysilicon (poly-Si) layer for the control gate (CG). It was also found that the poly-Si depletion gives deterioration in the program performance. This work...
We have investigated a new program disturb phenomenon by DIBL (drain-induced barrier lowering) in MLC NAND Flash device. It is found that lower programmed state cell shows large DIBL effect and its BVdss measurement results in unwanted programming of nearby erased state cells. It is attributed to punch-through leakage of programmed state cell during BVdss measurement. Electrons from this leakage are...
A new self-boosting phenomenon is observed in 51 nm NAND flash devices. The authors have modeled and named this observation 'local self-boosting by source/drain depletion cutoff, a result of low net N-type dopant in the source/drain region. As cell-to-cell design rules shrink into the 50-nm range, channel dopant is increased to reduce short-channel effects while implantation-related source/drain dopant...
One of the most important performances of NAND flash memory is reliability characteristics, such as program/erase cycling and data retention. Tunnel oxide quality is essential to the reliability and it is well known that tunnel oxide degradation during FN (Fowler-Nordheim) stress is due to the oxide trap and interface trap generation. It is believed that trapping mainly occurs where tunnel oxide is...
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