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In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported...
Microstructure variation with post-patterning dielectric aspect ratio (AR) and post-plating annealing temperature has been investigated in Cu narrow wires. As compared to the conventional annealing at 100 ◦C for a feature AR of 2.6, both elevated temperature anneals and reduced AR structures modulated Cu microstructure, which then resulted in a reduced rate of electrical resistivity increase with...
Middle-of-the-line (MOL) interconnect and contact resistances represent significant impacts to high-end IC performance at ≤ 10 nm nodes. CVD W-based metallization has been used for all nodes since the inception of damascene. However, it is now being severely challenged due to limited scaling of the traditional PVD Ti/CVD TiN barrier and ALD nucleation layers. This study reports the use of alternate...
A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.
This paper analyses the impact of 10nm Si cap layer for UTBB pFET eSiGe, with 35% Ge in channel and source/drain. For the first time, it is found that this Si cap can improve both access resistance and hole mobility in narrow structures.
UV cure on robust low-k with sub-nm pore and high carbon content (R-ELK=Robust ELK) was studied to enhance the modulus of the film. UV cure helps to create Si-CH2-Si bridging bond, which plays a role to enhance the modulus. UV cure does not affect the advantage of low PID (plasma-induced damage) and it was confirmed by Cint (interconnect capacitance) measurement for 80 nm pitch interconnect. Besides,...
This work demonstrates the building of 64 nm pitch copper single and dual damascene interconnects using pitch split double patterning scheme to enable sub 80nm pitch patterning. A self-aligned-via (SAV) litho/RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. An undercut free post RIE trench profile enabled the good metal...
The random formation of micrometric crystals on Al bonding pads can be an issue affecting wire bonding metal pad quality. The dry etch chemistry used to remove final passivation dielectric layers from the top of the bonding Al pad area is in fact based mainly on fluorine-containing gases (such as CF 4 , CHF 3 , etc.) which can leave fluorine as a residual on the metal pad surface as...
AEROSPATIALE has been involved for many years in the field of developing, manufacturing and assembling of launchers and reentry vehicles, either for civilian or military customers.More precisely, an important part of AEROSPATIALE activity has been related to the development of ablative materials for Thermal Protection Systems (HUYGENS, ARD, CTV studies, Mars Express, ...)These thermal protection materials...
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