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3D integration comes with the introduction of many new processes and materials that may affect behavior and reliability of the overall system. For reliability testing of 3D integration technologies a 3-level test chip has been designed that includes Through Silicon Vias (TSV's) and assembly layers and that allows evaluation of yield and electrical parameters under steady state (DC) and RF signal conditions...
Porous low-k dielectrics integration in interconnects is required to keep improving Integrated Circuits performance. However, these materials are highly sensitive to plasma processes and may be damaged during the patterning steps. Characterizing the plasma induced modification is required on patterned structures to develop less damaging plasma processes. Scatterometric Porosimetry (SP) has recently...
This paper presents the integration of dense (2.5 1012 CNTs/cm2) Carbon Nanotubes in via structures for future microelectronic interconnects generations. Process steps performed after CNT growth in vias are studied. Two different CNT encapsulation layers are evaluated (ALD Al2O3 and spin on resist). After polishing, well planarized CNTs vias structures are obtained in both cases. Post CMP clean is...
We investigated the mechanism of resistivity decrease in networked-nanographite wires. The wires had no failure during over 200 hours under a current density of 5E5A/cm2 at about 400°C. However, their resistivity decreased gradually owing to thermal stress. Raman and x-ray photoelectron spectroscopy revealed that the decrease in resistivity can be attributed to an increase in sp2 bonding corresponding...
The ruthenium (Ru) liner based metallization scheme depends on the ability to electrodeposit Cu onto thin, resistive Ru substrates with substantially high Cu nuclei density. In the present paper, a novel electrochemical bath that utilizes Cu-complexing agents to improve the nucleation of plated Cu films on Ru is presented. Such chemistries can generate Cu nucleation density on Ru greater than 1012...
In this paper the challenges and opportunities of a wafer fab process transfer are explained. Details and background of methodologies and choices made in the transfer of the back-end-of-line of a state-of-the-art SOI automotive process are explained. Field reliability results validate the choices made.
The integration of Carbon Nanotubes (CNT) in contact holes with TiN underlayer using CMOS compatible processes is discussed. Each process step was optimized by evaluating the electrical results obtained with contact test structures. Subsequently, this process was transferred to 150 nm diameter contact holes. We present the first electrical data obtained from automated probing of 150 nm diameter contacts...
Extrinsic failure behavior of vias and dielectrics in the backend of line (BEOL) has been studied using dedicated test structures on a large scale. Via fails after (unbiased) stress were detected utilizing a test set-up and program that allows the readout of more than 109 individual vias per wafer. The isolation behavior of intra and inter level BEOL dielectrics was studied by performing breakdown...
Two different material-selective Self assembled monolayers (SAMs) were successfully deposited on Cu and SiO2 structures that mimic the Dual Damascene integration scheme. A two-step SAM coating process is presented. First, a “sacrificial” SAM is deposited at the Cu bottom and secondly, a “barrier” SAM at the SiO2 surface. The order in the SAMs deposition sequence and the differential thermal release...
In this article the metallization schemes of output DMOS drivers for automotive SmartPower integrated circuits (ICs) are discussed. In contrast to non-automotive applications the main concern is the thermal-mechanical stability of the metallization during inductive switching which leads to high thermal pulses within the metallization. These pulses can result in junction temperatures above 400°C. Additionally,...
To overcome the energy dissipation limit facing virtually all field-effect devices including CMOS switches, there is a global search for devices using alternate state variables as the token of information. In this paper, physical models for latency and energy dissipation associated with various transport mechanisms are reviewed. Using stochastic wire length distribution models based on Rent's rule,...
In this study Ru-Mn alloys are discussed in terms of some of the major questions that are typically associated with the development of new types of barriers. First, the Cu diffusion barrier performance after annealing at high temperatures and under subsequent bias temperature stress is investigated, on SiO2 and on low-k dielectrics. Second, the origin of the barrier performance - either a self forming...
In the present paper, the use of high aspect ratio metallic nanowires (NWs) as functional interconnects between three-dimensionally stacked chips is proposed. First practical preparation steps, as there are the preparation of templates and the deposition of Ag-NWs, are presented. Later on, the applicational technology for vertically aligned NWs is proposed as their embedment into a polymer matrix...
50% Line Edge Roughness (LER) correlation has been observed after spacer formation in 20nm half pitch (HP) interconnects using Spacer- Defined Double Patterning (SDDP) approach. This correlation has a positive impact on Time-Dependent Dielectric Breakdown (TDDB) lifetime, which was also predicted by simulations. Comparison of TDDB lifetime for SDDP patterned 20nm HP and Litho-Etch-Litho-Etch (LELE)...
In this work, (1) we propose a new, simpler, and fully CMOS-compatible TiN\HfO2\TiN material stack, using PEALD TiN which after plasma optimization results in functional cells down to 2275nm2 (35nm×65nm), (2) we demonstrate stable switching between resistances >105Ω using a low program current of ∼1µA, where the 105Ω-resistive LRS state shows good retention at high temperature, projected to 10...
As interconnect dimensions decrease, the resistivity of copper increases dramatically because of electron scattering from surfaces, impurities, and grain boundaries (GBs), and threatens to stymie continued device scaling. Here we directly measure individual GB resistances in copper nanowires with a one-to-one correspondence to the GB structure. The resistance of high symmetry coincidence GBs is then...
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