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Ion beam milling is successfully implemented for smoothing roughness of the fin sidewalls for the FinFETs with poly-crystalline TiN metal gate (MG). The Vt variability is improved significantly by smoothing the fin roughness without degradation of the carrier mobility. The suppressed Vt variability is interpreted as improved uniformity in the grain orientation of TiN which causes work function variation...
This paper reports the positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel field-effect transistors (TFETs) with high-k gate stacks. The subthreshold slope (SS) is not degraded at all while the threshold voltage (Vth) shifts in the positive direction by the PBTI stress. The activation energy of ΔVth for TFETs is almost the same as FinFETs, indicating that the...
The impact of heated ion implantation (I/I) technology on metal-gate (MG)/high-k (HK) CMOS SOI FinFET performance and reliability has been thoroughly investigated. It was demonstrated that heated I/I brings perfect crystallization after annealing even in ultrathin Si channel. For the first time, it was found that heated I/I dramatically improves the characteristics such as Ion-Ioff, Vth variability,...
The scaled FinFET flash memories with an oxidenitride-oxide (ONO) charge trapping (CT) layer have actively been developed in the past few years owing to the excellent short-channel effect (SCE) immunity of the FinFET [1, 2]. As a high-k dielectric blocking layer, an Al2O3 layer has also been used in the bulk FinFET flash memories [3]. Very recently, we have also developed floating-gate (FG) type SOI-FinFET...
Performance of a double-gate (DG) FinFET in the cryogenic environment is discussed based on measurements and simulation. It was found that the DG FinFET has an excellent immunity to the kink effect in the cryogenic environment. Our physics-based compact model reproduced the measured I–V characteristics. The successful demonstration of an opamp consisting of the DG FinFETs at 4.2 K is also presented.
It is well known that 3D channel devices, such as double-gate (DG) and tri-gate (TG) FinFETs, provide excellent short-channel effect (SCE) immunity. Thus, the scaled 3D channel FinFET flash memories with oxide-nitride-oxide (ONO) charge trapping layers have actively been developed [1–3]. Very recently, we have also developed floating-gate (FG) type SOI-FinFET flash memories [4–7]. In this paper, we...
We experimentally investigated the device performance of n+- poly-Si/PVD-TiN stacked gate FinFETs with different Hfin's. It was found that mobility enhances in the tall Hfin devices due to the increased tensile stress. However, as Lg decreases, Ion for tall Hfin case becomes worse probably due to high Rsp. It was also confirmed that Vth variation increases with increasing Hfin due to the rough etcing...
The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel...
One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper...
Influence of NiSi S/D incorporation on parasitic resistance (Rpara) fluctuation of FinFETs was investigated in detail. While the NiSi S/D enhances the on current of the FinFET thanks to the Rpara reduction, it also causes additional Rpara fluctuation. Through analysis of correlation of Rpara with fin thickness and gate-to-NiSi offset fluctuation, it is revealed that NiSi/n+-Si contact resistance component...
An adaptive-threshold-voltage differential pair and a low-voltage source follower using independent-double-gate-(IDG-) FinFETs are proposed for a low-voltage operational amplifier (op amp). These circuits were implemented by our FinFET technology that enables co-integration of connected-DG- (CDG-) and IDG-FinFETs. The proposed components enable a two-stage op amp to accept the input below the nominal...
This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast...
PVD-TiN gate FinFET SRAM half-cells with different β-ratios and fin-height controlled transistors have successfully been fabricated using orientation-dependent wet etching and selective recess RIE. It was found that read static noise margin (SNM) increases significantly by controlling β from 1 to 2. With further increasing β, read SNM increases slightly. On the other hand, write margin shows weak...
The Vt variability in scaled FinFETs with gate length (Lg) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., work-function variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall...
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