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New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65nm CMOS process. 7 types of standard cells are measured with 60 DUT's for each type...
User customizable logic paper (UCLP) with a sea-of-transmission-gates (SOTG) of organic CMOS transistors is developed to enable users to fabricate custom integrated circuits by printing 200 ??m width interconnects with at-home ink-jet printers for educational purposes. Compared with the conventional gate array, the SOTG reduces the area of the circuits by 11 to 85%.
Regular fabric structure is expected to reduce the process variations and increase the yield in sub-micron technology regime. Few experimental assessments, however, for the effectiveness of the regular structures has been carried out yet. In this paper, three kinds of circuit blocks are implemented with four kinds of layout styles with different regularity, and the effect of regularity on the circuit...
The minimum operating voltage (VDDmin) of 90-nm CMOS ring oscillators (RO's) is investigated in order to clarify the lower limit of supply voltage (VDD) for logic circuits. The measured VDDmin is determined by the intra-die threshold voltage random variations and increased from 91 mV to 224 mV when the number of RO stages increased from 11 to 1001, which hinders the VDD scaling. Lowering VDDmin is...
A new low clock swing flip-flop (F/F) is proposed. The existing low clock-swing F/F's consume high power, introduce speed penalty due to contention currents or require large silicon area due to separate well for substrate biasing. By reducing contention currents, our proposal efficiently mitigates those issues. Measurements and simulations are carried out based on a 90 nm CMOS process, demonstrating...
A VDD-hopping accelerator for on-chip power supply circuits is proposed and the effectiveness of the accelerator circuit is experimentally verified. The circuit enables nano-second order transient time in on-chip distributed power supply systems. The measured transition time is less than 5ns with load circuit equivalent to 25k logic gates in 0.18-mum CMOS. This is to be compared with the case without...
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