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With the advancement of technology into the nanometer regime, the complexity of design at advanced technology has escalated exponentially. Notable areas of difficulty are timing closure, signal integrity, power optimization etc. Advanced foundries, with estimated close to 40% of worldwide 90nm tapeouts, are taking several initiatives to help designers make best use of the technologies to produce designs...
"T-engine" is an open platform for embedded systems in the ubiquitous computing age. It consists of standard real-time kernel, T-kernel, running on the standard hardware with networking facilities. It provides infrastructure for the embedded system development of highly networked and highly value-added products in a short period of time. Providing a standard platform for the ubiquitous computing...
For last three decades, semiconductor memory business has greatly grown due to the tremendous progress of electronic data processing (EDP) mainly led by outstanding evolution of PC technology. Recently, various mobile appliances such as hand-held phone, DCS, and MP3 drive new growth of semiconductor memory, which results in unprecedented demand of non-volatile memories, especially mass storage NAND...
This paper compares design concepts of 63nm-8Gb and 90nm-4Gb multilevel cell (MLC) NAND flash memory. For 8Gb MLC NAND flash memory, locations of peripheral circuits and charge pumps are determined to optimize area and signal speed. Page buffer is simplified by reducing the number of transistors with minimal connections thereby resulting in smaller size. Performance is improved by using fast-read/write...
A 16Mbit low power SRAM with 0.98mum2 cells using 0.15mum DRAM and TFT technology has been developed. A new type memory cell technology achieves enough low power, low cost and high soft error immunity without large investment. By these improved characteristics some customers at industrial machines and handy devices decided to use this new type of SRAM by compatibility with SRAM
A 4-way SIMD streaming processor of a cell processor is developed in a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the non-SRAM area. ISA, microarchitecture, and physical implementation are co-optimized to achieve a compact and power efficient design
This paper presents the first wireless LAN baseband LSI capable of transmitting high-definition audio with video (HD-A/V) content requiring secure content protection. The LSI fully complies with IEEE 802.11a, e, h, and i. The hybrid coordination function controlled channel access (HCCA) of 802.11e is employed to reserve the transmission period for HD-A/V content. In addition, the block acknowledgement...
A new circuit technique of deserializing for Gb/s serial communication such as "digital visual interface" for PC and "high-definition multimedia interface" for CE application is proposed. Vernier over sampling and alignment technique can achieve both low power and low bit error rate at high frequency operation in DVI/HDCP digital graphic communication receiver. VOSA circuit is...
This paper describes a wide band CDR with a new encoding scheme for a digital video data transmission. The CDR works from 105Mbps to 1365Mbps without any external frequency references. The proposed encoding scheme uses both PECT (periodic embedded clock transition) and PECT (periodic embedded clock period) scheme, and it helps the CDR's capture process. The CDR is using both digital and analog techniques...
This paper presents the design of a 2.5Gb/s serial link transceiver with a power consumption of 70mW. With IV supply voltage, the transceiver achieves the bit error rate of 10-14. A supply regulated PLL is shared by the transmitter and the receiver to facilitate the low-power and low-voltage design. The output jitter of the transmitter is 53.9ps peak-to-peak and the chip area is approximately 0.54...
A laser diode driver and a limiting amplifier for multirate and multistandard optical transceiver modules from 155Mb/s to 2.1Gb/s had been developed using a 0.5-mum SiGe BiCMOS technology. With new driving circuit, the laser can be DC-coupled to the laser diode driver for reduced component count and ease of multi-rate operation. Automatic power control (APC), modulation compensation and built-in temperature-compensation...
In this paper, a single channel clock-edge modulated serial link for mobile display interface is presented. Clock edge modulation (CEM) enables all necessary signals between a graphic processor and a LCD timing controller to be transferred over a single, DC-balanced differential channel, thus greatly saving the power and costs of the existing parallel lines. A simple DLL-based CEM decoder is described...
A 130nm 1.2V GTL bus interface with compensated slew rate and termination achieves 667MT/S 10.7GB/S data rate in a 3-load MP environment. The design utilizes preboost and postboost methods, current steering circuit to minimize simultaneous switching noise and negative hysteresis to speed up the common-clock delay. The design also incorporates system-level I/O loopback for system timing marginality...
This paper presents a high-speed LVDS I/O interface for mobile DRAMs. A data rate of 6Gbps/pin and a transmit-jitter of 57.31ps pk-pk were demonstrated, in which an 800MHz clock and a 200mV swing were used. The power consumption by I/O circuit is 6.2mW/pin when a 10pf load is connected to the I/O, and output supply voltage is 1.2V. The proposed mobile DRAM has 6 data pins and 4 address/command pins...
This paper presents an all digital low voltage differential signal (LVDS) driver for serial-ATA (SATA-II) with simultaneous switching noise (SSN) reduction capability. An auto calibration mechanism is included to deal with the process and environmental variation. The chip is implemented using TSMC 0.18-mum 1P6M CMOS technology. The core area is 350times350 mum2. The transmitter operates at 3 Gbps...
We present a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC) using a new digital distortion calibration technique. The calibration parameters are obtained using the same system as the conventional digital gain calibration. The ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. With the calibration it achieves 15-dB improvement of the third-order nonlinearity...
This paper presents a reconstructive oscillator based sinusoidal signal generator which can produce both high and low frequency signals by switching the oscillator into different mode. In addition, analog and digital signals can be produced concurrently in both modes. Also, signal amplitude and oscillation frequency can be precisely controlled compared with pure analog signal generator. Except for...
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