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In this paper, we show the process and integration results of small TSVs integrated by 300mm 3DIC BTSV process. The TSV size is from 2um to 3um (in diameter) with aspect ratio of 10. The achievements of this work are: 1) successful demonstration of 20um thin wafer process by ITRI's 300mm wafer thinning process; 2) 2∼3um TSV patterning and etching performed by backside TSV process; 3) Combination of...
In this research, the wafer level Cu/BCB hybrid bonding with TSV for 3D integration by using fly cutting technology is proposed. As we know Cu bump surface is rough by electroplating, and BCB is spin-coated on Cu bump wafer induced high topography. Cu bump surface roughness and Cu/BCB co-planarization are improved by fly cutting to achieve good Cu to Cu and BCB to BCB bonding interface without any...
Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In...
In this research, a backside illuminated CMOS image sensor (BSI-CIS) without through-silicon via and TSV based Si interposer are developed with thin wafer handling technology. The BSI-CIS wafer is implemented front-side processes then temporary bonded on a Si carrier by using ZoneBOND™ technology. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent...
Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based...
One 4-Ch × 2.5 Gbps rigid-flex opto-electrical link integrated with two connectors, one transmitter, one receiver, one rigid-flex PCB was demonstrated. One optical waveguide film was separately fabricated and laminated in the flex PCB, and the optical assembly tolerance of alignment system is maintained less than 5 urn. Optical coupling from optical devices of transmitter into the waveguides and transmit...
As high-speed, high-density, and high-performance are the primary IC development targets, packaging technologies play a key role to bring out the best performance of those ICs. In this paper, an active component formed by an active chip embedded technology is developed for the package of a high speed DDR2 memory device. Embedding of semiconductor chips into an organic substrate provide a solution...
Flexible electronic system package technology was developed to meet the needs of flexible application. Because of the flexible characteristic, the package can be attached to a flat, curve surface and even a dynamic surface. It is important to provide protection of ultra-thin semiconductor chip and integrate these chips with flexible substrate. The aim of this paper is to develop an ultra-thin film...
This paper discloses an ultra-thin and highly flexible package with embedded active chips. In this structure, there are no any supporting and permanent substrates needed. A 3 um copper foil with 18 um carrier layer was used as temporal substrate. The carrier layer will be removed after chip embedded process. After patterning and etching processes, the temporal copper foil became the bottom circuit...
In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through...
To prevent potential yield loss, achieve TSV with higher aspect ratio, improve the bonding reliability, and reduce the process cost, a clamped through silicon via (C-TSV) interconnection for stacked chip bonding is proposed and developed in this paper. The metal cap on pad design can not only be a bonding layer for other stacked die on it, but also performs as a protection stopper for blind vias drilled...
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