The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Today's explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to planar NAND and is quickly displacing planar NAND in the SSD market, due to its performance, reliability, and cost competitiveness. V-NAND has also eliminated...
In this paper, the channel stacked array (CSTAR) NAND flash memory with layer selection by multi-level operation (LSM) of string select transistor (SST) is proposed and investigated to solve problems of conventional channel stacked array. In case of LSM architecture, the stacked layers can be distinguished by combinations of multi-level states of SST and string select line (SSL) bias. Due to the layer...
In this study, the gate-all-around (GAA) poly-Si channel flash memories with charge trap layer (Si3N4) have been successfully fabricated. Electric characteristics of fabricated devices including threshold voltage shift with program/erase operation have been investigated. Gate configurations were structured differently according to each defined channel width. Results show that devices with gate-all-around...
In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory...
Recently, 3D stacked NAND flash architectures have been proposed to solve scaling limit of the planar NAND flash memory based on floating-gate type [1]-[2]. However, theses structures have several drawbacks. For TCAT[1], declined hole-etch slope leads to different curvature radius of each stacked active layers. Consequently, different elecric field is applied to each layer in program operation, which...
Modern VLSI technology has been developed with continuous scaling of MOSFET. However, as MOSFET has been scaled down, a lot of critical issues have risen and resulted in a considerable degradation of individual devices [1]. On the other hand, owing to its periodic on/off characteristic, single-electron transistor (SET) attracts attention with its promising performance. But, in general, fabricating...
Supply voltage (VDD) scaling has been an important issue as the CMOS scaling down. Scaling of devices induces large leakage current due to Short Channel Effects (SCEs). Also, Subthrehold Swing (SS) value of CMOS devices is theoretically limited to 60 mV/dec. Various structures have been proposed to overcome power dissipation problems, one of which is the TFETs [1–2]. However, TFET has two critical...
As the needs for high density NAND flash memory have been dramatically increasing, the memory density has also increased by scaling down the technology node. As the scaling of NAND flash memory is accelerated, the short channel effect is more severe and further scaling down is faced with process limitations. So, various types of 3D stacked NAND flash memory has been introduced and reported for ultra-high-density...
In this study, the influence of sidewall thickness on the threshold voltage and on-current of L-shaped Impact-ionization metal-oxide-semiconductor transistor (I-MOS) is investigated. For the sidewall thickness in the range of 10 nm to 20 nm, the devices of thicker sidewall show lower on-current and higher threshold voltage. This is because the electron concentration between the channel and the most...
With the device dimension scaling down, thickness-dependent property optimization for Oxide-Nitride-Oxide (ONO) used in SONOS flash memory is an important issue for the compatibility with scaled CMOS technology. With regard to the thickness-dependent property, trap-based erase behaviors should be investigated thoroughly because electron back-tunneling from gate make erase operation difficult. This...
Since recent mobile electronic devices have started to adopt NAND flash memory as their main data storage device, the demand for low cost and high density NAND flash memory has been rapidly increasing. As a promising candidate, nanowire SONOS NAND flash memory array has been introduced and reported for highly scalable device structure. However, since it is hard to bias floating body of memory cells,...
In order to implement more advanced nonvolatile memory device, many studies have been devoted to improve program/erase speed, endurance, and retention characteristics of nitride-based SONOS flash memory. As the CMOS device size shrinks down, the oxide-nitride-oxide (ONO) multi-layer where charge storage takes place in discrete traps in the silicon nitride layer needs the optimization of thickness...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.