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The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to...
Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling...
This paper shows for the first time, the influence of back gate bias (VB) in some analog parameters on pMOS Silicon-On-Insulator (SOI) omega-gate nanowire (ΩG-NW) devices down to 10 nm width (W). An excellent electrostatic control is observed in devices down to 40 nm of channel length. The saturated transconductance slightly increase while the output conductance slightly decrease with VB increment,...
We investigate for the first time the influence of the back gate bias (VB) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative VB the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive...
Motivated by the TFET (tunneling field effect transistor) technology, we investigate the temperature and gate overlap/underlap influence on the capacitance of p-i-n diodes fabricated with UTBB FDSOI. The underlap-overlap architecture modifies the split capacitance curves essentially when the back interface is depleted. As a result, the extracted front gate oxide (tOX) and silicon film thickness (tSi)...
The characterization of low-frequency (LF) noise is carried out in p-type Si passivated Ge FinFETs, comparing the performance of narrow (Wfin = 20 nm) and planar-like (Wfin = 100 nm) devices. The low-frequency noise is shown to be dominated by flicker noise, i.e., (1/fγ) where γ∼1, in the evaluated frequency range for both fin widths, which is governed by number fluctuations. Furthermore, narrow devices...
This paper presents for the first time an experimental analysis of germanium pMOSFETs operating in conventional, dynamic threshold voltage (DT, where VBS = VGS) and enhanced dynamic threshold voltage (eDT, where VBS=k*VGS) modes. In addition, there are two different HfO2/Al2O3 gate stack thicknesses under evaluation. The subthreshold swing (SS) improves 60% in eDT (k = 2) mode compared to the conventional...
The goal of this work is to study parameters related to the analog performance of tunnel field effect transistors (TFETs). The obtained results have been analyzed in terms of temperature variation (ranging from 25°C to 150°C) and source composition (Sh-xGex and 100% Si). The first part is focused on characteristic curves of the drain current as a function of gate voltage and drain voltage. Next step...
This paper presents an experimental comparison of the analog performance between a triple-gate FinFET fabricated on Bulk (BFF) and on Silicon-On-Insulator — SOI (SFF) substrates. This comparison was performed based on the drain current, subthreshold swing, transconductance, output conductance and finally the intrinsic voltage gain. For narrow fin width, the SFF presents better performance than BFF,...
In this paper, the floating body effect (FBE) is experimentally investigated on triple gate n-channel Bulk FinFETs for 1T-FBRAM (1 transistor Floating Body Dynamic Random Access Memory) application. A difference between the Direct Current (DC) and the Alternating Current (AC) measurements corresponding with the real memory operation is shown. The large hysteresis under DC measurement related to floating...
This paper investigates the ground plane influence on Ultra Thin Body and Buried Oxide (UTBB) FDSOI devices applied in a dynamic threshold voltage (DT) operation (VB=VG) over the conventional one (VB=0V). The ground plane in enhanced DT (eDT), where the back gate bias is a multiple value of the front gate one (VB=k×VG) and the inverse eDT mode (VG=k×VB) were also considered and compared to the other...
This study presents an experimental analysis of the Xray radiation effect on the drain induced barrier lowering (OIBL) of strained and unstrained, p and n type triple gate SOI MuGFETs. In both types of devices, the narrow fin transistors are more immune to radiation because of the better coupling among the gates. It is shown that total dose damage in nMuGFETs always leads to a performance degradation,...
In this work the pTFET is evaluated from analog application point of view, through a direct comparison with the well-known pFinFET performance. This evaluation is mainly focused on the intrinsic voltage gain and the unity gain frequency. Although the total capacitance of FinFETs showed to be worse than for pTFETs, the transconductance behavior plays the main role and results in a higher unity gain...
The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower bandgap and higher BTBT predominance), the NW-TFETs with 27% Ge source present a better intrinsic voltage gain...
In this work the back bias influence on the analog performance of tunnel-FETs is evaluated experimentally for the first time. The analysis of the transconductance, output conductance and intrinsic voltage gain (Av) was performed by comparing the pTFET behavior with a well-known pFinFET that was fabricated using the same process flow. Numerical simulations were also performed in order to explain the...
The dependence of the activation energy on the electric field is investigated in extensionless (underlap) UTBOX FDSOI applied as a single transistor floating body RAM. It was found that with the same gate stack it is possible to extract two different activation energies when the electric field in the hold condition is different. Higher barrier lowering induced by elevated electric field implies in...
The triple-gate MuGFET is nowadays one of the most important contenders for sub 22 nm MOSFET generation due to excellent control of gate on the channel [1]. Additionally to the better control provided by tri-gate structure, the use of controlled mechanical stress is largely used for boosting the carrier mobility. Biaxial strain is more effective for longer and wider devices due to the relaxation of...
A single transistor 1T-DRAM, also called Floating-Body RAM cell (FBRAM) makes use of the transistor floating body as a charge storage node. Nowadays, it has become of high interest because it overcomes the integration problems associated with the capacitor of the conventional 1T/1C DRAM. In order to improve the retention time and sense margin, the parasitic BJT (Gen2) programming shows the best performance...
The continuous reduction of the devices has driven the scientific community to explore alternative technologies that are compatible with CMOS technology, but with different operating principles. The Tunnel Field Effect Transistors (TFETs) are a new conception of devices that have been proposed as a promising option to replace conventional MOSFETs, since its physical structure allows a very steep subthreshold...
The stringent requirements imposed by the ITRS rely on the introduction of alternative and/or new gate concepts and the implementation of advanced processing modules and materials[1]. During the last decade, alternative gate concepts, with an evolution from planar single gate to double gate, multi-gate FET (MugFET) or FinFET, and gate-all-around (GAA) or nanowire concepts have been extensively studied...
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