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The characterization of low-frequency (LF) noise is carried out in p-type Si passivated Ge FinFETs, comparing the performance of narrow (Wfin = 20 nm) and planar-like (Wfin = 100 nm) devices. The low-frequency noise is shown to be dominated by flicker noise, i.e., (1/fγ) where γ∼1, in the evaluated frequency range for both fin widths, which is governed by number fluctuations. Furthermore, narrow devices...
This paper presents an experimental comparison of the analog performance between a triple-gate FinFET fabricated on Bulk (BFF) and on Silicon-On-Insulator — SOI (SFF) substrates. This comparison was performed based on the drain current, subthreshold swing, transconductance, output conductance and finally the intrinsic voltage gain. For narrow fin width, the SFF presents better performance than BFF,...
In this paper, the floating body effect (FBE) is experimentally investigated on triple gate n-channel Bulk FinFETs for 1T-FBRAM (1 transistor Floating Body Dynamic Random Access Memory) application. A difference between the Direct Current (DC) and the Alternating Current (AC) measurements corresponding with the real memory operation is shown. The large hysteresis under DC measurement related to floating...
In this work the pTFET is evaluated from analog application point of view, through a direct comparison with the well-known pFinFET performance. This evaluation is mainly focused on the intrinsic voltage gain and the unity gain frequency. Although the total capacitance of FinFETs showed to be worse than for pTFETs, the transconductance behavior plays the main role and results in a higher unity gain...
In this work the back bias influence on the analog performance of tunnel-FETs is evaluated experimentally for the first time. The analysis of the transconductance, output conductance and intrinsic voltage gain (Av) was performed by comparing the pTFET behavior with a well-known pFinFET that was fabricated using the same process flow. Numerical simulations were also performed in order to explain the...
The stringent requirements imposed by the ITRS rely on the introduction of alternative and/or new gate concepts and the implementation of advanced processing modules and materials[1]. During the last decade, alternative gate concepts, with an evolution from planar single gate to double gate, multi-gate FET (MugFET) or FinFET, and gate-all-around (GAA) or nanowire concepts have been extensively studied...
In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple gate FinFETs. The threshold voltage, subthreshold swing, transconductance, conductance, resistance and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. The results indicate that the DTMOS FinFET structure...
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