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This paper presents 64-quadrature amplitude modulation (QAM) 60-GHz CMOS transceivers with four-channel bonding capability, which can be categorized into a one-stream transceiver and a two-stream frequency-interleaved (FI) transceiver. The transceivers are both fabricated in a standard 65-nm CMOS technology. For the proposed one-stream transceiver, the TX-to-RX error vector magnitude (EVM) is less...
This paper describes a digital-mapping DDFS with a frequency tuning and amplitude resolutions of 24-bits and 10-bits respectively. This Si-CMOS-MMIC is the first solution supporting a sampling rate of 7GS/s and frequency, phase and amplitude modulations in the digital domain. It includes a 14-bits pipelined ripple-carry adder and a 10-bits high-speed multiplier for phase and amplitude modulations...
This paper describes a Digital-Mapping Direct Digital Frequency Synthesizer consuming only 118 mW when operating at 2 GS/s in 65nm CMOS. The active area is 0.142 mm2 with an accumulator size and amplitude resolution of 24 and 10 bits respectively. The Spurious-Free Dynamic Range is better than 41 dBc for synthesized frequencies below 750 MHz and 30 dBc over the entire Nyquist bandwidth. The Power...
The adoption of charge-redistribution-technique-based successive approximation register (SAR) architecture in capacitance domain has improved the performance of the digital readout circuit used for capacitive sensor applications. The direct conversion of an off-chip sensor's capacitance to a digital value requires a large implemented capacitor array. A scale factor scaling the reference voltage is...
A 7GS/s DDFS MMIC featuring a Two-Times Interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for Random Swapping Thermometer Coding Dynamic Element Matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz...
L-2L de-embedding method was proved accurate at millimeter-wave (mm-wave) frequencies around 60GHz. However, it was never quantitatively compared to a more complicated method at frequencies as high as 100GHz. In this paper, L-2L and TRL de-embedding methods are compared by applying both on test structures fabricated using CMOS 65nm process. More focus will be given to the W-band frequencies by comparing...
This paper presents a frequency doubler that operates at W-band and D-band frequencies between 100GHz to 123GHz. An optimized buffering method is proposed to achieve saturated output power as high as 5.5dBm with over 60dBc rejection of the fundamental frequency at −8dBm input power. The overall circuit power consumption is 116mW. The doubler was designed and implemented using 65nm CMOS technology.
A 60GHz integrated antenna switching architecture is presented for millimeter-wave transceiver system. This circuit topology re-uses the last stage's transistor of power amplifier (PA) and the first stage's transistor of low-noise amplifier (LNA) as the switching elements, and the matching blocks for PA and LNA. A two-stage LNA and a two-stage PA integrated together as antenna switch is fabricated...
This paper proposes a pulse-tail-feedback technique for improving both 1/f2 and 1/f3 noises. The proposed VCO has separated tail transistors driven by inverters with rail-to-rail voltage swing. The tail transistor has an impulse shaped current waveform to improve FoM, and the flicker noise up-conversion is reduced by the switching operation. A prototype of the proposed VCO is implemented in 180nm...
A novel high-data-rate low-power spectrum-efficient 60GHz Bi-Phase-On-Off-Keying (BPOOK) transceiver is presented for indoor short-range IoT application targeting the common 60GHz spectrum mask used in IEEE 802.11ad/ WiGig standards. By employing bi-phase encoder and double-balanced mixer, the BPOOK transmitter spectrum is efficient to be compliant with 2-channel bonding spectrum mask. The proposed...
This paper proposes a noise shaping SAR ADC with open-loop integrator using dynamic amplifier. The proposed integrator for a delta-sigma modulator requires low-gain open-loop amplifiers, therefore low power dynamic amplifier can be used. Moreover, binary-mode dynamic element matching is proposed to overcome the nonlinearity of a capacitor DAC. An SNDR of 83.5 dB, a power consumption 273.4 μW, and...
The 60GHz carrier with 9GHz bandwidth enables ultra-high-speed wireless communication in recent years [1–4]. To meet the demand from rapidly-increasing data traffic, the IEEE802.11ay standard is one of the most promising candidates aiming for 100Gb/s data-rate. Both higher-order digital modulation such as 128QAM and channel bonding at 60GHz are considered to be used in the IEEE802.11ay standard. However,...
This paper presents a supply regulated synthesizable injection-locked PLL (IL-PLL), using a noise-isolation LDO. The noise-isolation LDO realizes a time-shift operation to isolate the PLL from both supply and LDO noise, so the IL-PLL operation remains robust, even within a noisy SoC. The core layout of the PLL is implemented using solely a foundry provided standard-cell library for a 65nm CMOS process...
A W-band ultra-high data-rate (56Gb/s) wideband (68–102GHz) 65nm bulk CMOS wireless transceiver is presented. Frequency interleaving by two up-converted IF data signals using 68 and 102GHz LO to W-band is applied to achieve wideband and a world-record 56Gb/s wireless communications on CMOS. 16QAM modulation is used for 6.5GHz (26Gb/s) low-band and 7.5GHz (30Gb/s) high-band data. Transmitter/receiver...
This paper presents an HDL-synthesized injection-locked phase-locked loop using LC-based DCO for on-chip clock generation. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm CMOS process, this prototype demonstrates a 0.142ps integrated jitter at 3.0GHz and consumes 4.6mW while only occupying...
A low-power and small-area 60-GHz CMOS transmitter with oscillator pulling mitigation is presented. The subharmonic injection locking technique for the suppression of pulling effects is analyzed and demonstrated. The transmitter fabricated in a 65nm CMOS process achieves 7.04-Gb/s data rate with an EVM performance of −25 dB in 16QAM. The whole transmitter consumes 210 mW from a 1.2-V supply and occupies...
This paper presents a dynamic pipelined analog-to-digital converter (ADC). A time-domain linearization technique is proposed to enhance the linearity of dynamic amplifiers. Also, an inverter threshold voltage based method is proposed to calibrate the common mode voltage of the dynamic amplifier. Furthermore, a capacitor digital-to-analog converter (CDAC) based method is used to calibrate the stage-gain...
An opamp-free solution to implement 2nd order noise shaping in a successive approximation register analog-to-digital converter is presented. This 2nd order fully-passive noise shaping, which has high power efficiency, is realized by charge-redistribution. A gain of 2 is required in this proposal which is realized by a passive method to save power. A prototype chip is fabricated in a 65-nm CMOS process...
In this paper, a CMOS tail-filtering VCO using Helium-3 ion irradiated Q-enhanced inductors is presented. The prototype of this VCO is implemented in a standard 65-nm CMOS process. An improvement of approximately 2.5dB in FoM is achieved after the Helium-3 ion irradiation because of the inductor quality factor improvement. The VCO achieves a phase noise of −116.4dBc/Hz at 1MHz offset while only consuming...
This paper discusses mm-wave CMOS transceiver IC design focusing on the techniques to increase the transmission data rate. Basic design key points are the increase of bandwidth, the increase of SNR, the decrease of phase noise in quadrature oscillator and frequency interleaving technique. Thus we selected the direct conversion architecture with resistive feedback amplifier to realize the wideband...
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