The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The high integration of current silicon devices leads to growing transient failure rates for multi-core based embedded systems. As a consequence, we can develop on-chip fault tolerance solutions to increase the reliability of Multi-Processor Systems-on-a-Chip (MPSoCs), for instance, the active redundancy of cores (e.g., on-chip Triple Modular Redundancy) which requires independence among the replicated...
Current embedded systems offer enough performance to integrate on a single chip jobs that required several distributed devices in the past. The execution environment of such an integrated architecture should satisfy key requirements, such as, temporal predictability, fault containment or flexibility. In this paper we present these requirements and argue about the suitability of embedded hypervisors...
This paper describes a novel scheduling algorithm for the execution of hardware tasks with real-time constraints onto partially and dynamically reconfigurable FPGAs. The Area-Time response Balancing scheduling algorithm (ATB) is inspired by the well-known Earliest Deadline First (EDF) algorithm, which is extended with a technique for reducing the fragmentation on FPGA's reconfigurable area. This technique...
An Autonomous Fault-Tolerant System (AFTS) refers to a system that is able to configure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain its functionality. This work analyzes how AFTS could be built, specifically focusing on hardware platform dependant issues, and gives an overview of the state-of-the-art in...
This paper presents a new single event upset (SEU), multiple bit upset (MBU) and single hardware error (SHE) mitigation strategy to be used in Virtex-4 FPGAs. This strategy aims to increase not only the effectiveness of traditional triple module redundancy (TMR), but also the overall system availability. Frame readback with ECC detection and frame scrubbing are combined in a dynamically reconfigurable...
The standardization of train communications protocols, train communication network (TCN), has created a need to design new electronic devices which can communicate according to them. Up to date, several solutions have been suggested, but every one needs additional circuits. In this article we present a novel flexible architecture which allows the materialization of slave nodes for multifunction vehicle...
This work presents an image recognition technique that enables finger position to be automatically detected in natural interaction systems, within the context of ambient intelligence, AmI. The aim is a robust system in which users do not need to wear gloves containing specific colored markings to establish location. The system has been validated, having been used for the design of a virtual keyboard...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.