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This paper presents a quad-lane serial link that supports virtually all data center system-side and line-side communications standards from 8.5–13 Gbps, implemented in 28 nm CMOS. The Tx is series source terminated with a 4-tap FFE. Its swing ranges from 33 mV to 1 Vppd. The Rx has CTLE, 5-tap DFE and CDR with 2x-oversampling, and baud-rate timing recovery options. At 13 Gbps, the link can equalize...
At data rates beyond 10Gb/s, most wireline links employ NRZ signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more severe and do not benefit from process scaling in the same fashion that circuit design does. Reflections from impedance discontinuities in the PCB and package...
A quad-channel, 112–128 Gb/s coherent DP-QPSK transmitter in 40 nm CMOS is presented. The 27.9–32.1 Gb/s TX features a half-rate architecture with a 2-tap FIR. The measured output has an amplitude of 1.2Vpp-diff with 1.3 ps deterministic jitter (DJ). The DP-QPSK TX's precoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing...
Network traffic speeds are increasing to meet the demands of data centers and network operators to support data-rich services like video streaming and social media. This has accelerated the adoption of 100Gb/s connectivity from the present 10Gb/s and 40Gb/s rates. One challenge that remains is the high power consumption of 100Gb/s systems. As mentioned in [1], power dissipation of the 100GbE gearbox...
The introduction of 40Gb/s networks, spurred by 40Gb/s WDM growth, can alleviate bandwidth bottlenecks of Internet infrastructure while simultaneously reducing operating costs. Increasingly, standard CMOS technology is used to enable transceiver speeds [1–5] previously achievable only by using expensive bipolar technology. However, at 40Gb/s, limited channel bandwidth coupled with stringent receiver...
This paper presents a wide-band analog Fractional-N clock synthesizer operating from 8 to 12.4GHz suited for data communication standards. The synthesizer generates a low noise clock with rms jitter of 288–460fs, yet maintains wide loop bandwidth from 1.5 to 4.3MHz. The design consumes 16.9mW from a 1V supply, while occupying an area of 0.39mm2 in a 40nm CMOS technology.
Recently developed 40Gb/s optical modulation formats such as return-to-zero differential quadrature phase-shift keying (RZ-DQPSK) and carrier-suppressed return-to-zero differential quadrature phase-shift keying (CS-RZ-DQPSK) are promising, since they offer high optical signal-to-noise ratio, high transmission efficiency and can tolerate large chromatic dispersion [1, 2]. The recent advances in processing...
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