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In nanoscale FPGAs, variability and aging significantly limit performance. In this paper, a novel aging monitoring methodology for FPGA-based designs to mitigate those effects is proposed. Local sensors are embedded in the configured functionality, monitoring critical paths, at production or during product lifetime. No design freeze (slice and routing locked) is required. When sensors observe a user's...
The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval. The design procedure is described, including the constrained placement of some delay sensors. The proposed technique is particularly useful to...
In current nanometer technologies, aging effects (due for instance to Negative Bias Thermal Instability) may appear after relatively short operating times, compared to the expected lifetime of circuits, even for relatively short-cycle consumer electronics. Therefore, there is an increasing need for on-chip aging monitoring. This paper presents a programmable aging sensor that can be embedded in FPGA-based...
The implementation of complex, high-performance functionality in nano-CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This paper describes the application of semi-empirical propagation delay variation models to estimate the effect of process variations on the timing response...
The use of Real-Time Operating Systems (RTOSs) became an attractive solution to simplify the design of safety-critical real-time embedded systems. Due to their stringent constraints such as battery-powered, high-speed and low-voltage operation, these systems are often subject to transient faults originated from a large spectrum of noisy sources, among them, the conducted and radiated Electromagnetic...
In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-faults due to Power-supply disturbances in nanometer technologies. Using a previously proposed VT (power supply Voltage and Temperature)-aware time...
As IC technology scales down, signal integrity issues such as power supply noise and clock skews are becoming one of the major concerns of gigahertz system-on-chip (SoC) design. Considering that one of the most important mechanisms to degrade signal integrity is electromagnetic interference (EMI), this paper analyzes the effectiveness of a clock duty-cycle (CDC) modulation technique to enhance SoC...
The purpose of this paper is to present a new robust methodology for synchronous communications in a BUS, connecting multi-clock domains. Traditionally, when robust solutions are needed, an asynchronous communication is used. However, the low transfer rates associated with asynchronous solutions make them inadequate for high performance digital systems. On the other hand, synchronous communications...
As IC technology scales down, interconnect issues are becoming one of the major concerns of gigahertz system-on-chip (SoC) design. Voltage distortion (power supply noise) and delay violations (signal and clock skews) dramatically contribute to signal integrity loss. As a consequence, performance degradation, reliability problems and ultimately, functional error occur. In this paper, we propose a new...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (Vdd) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional tolerance, by dynamically controlling the instant of occurrence of the clock edge trigger driving specific memory cells. On-line, dynamic delay...
As IC technology scales down, power supply voltage and temperature variations play an increasing role in signal integrity loss, which lead to performance degradation, reliability problems and functional errors. In this paper, we propose a new methodology to improve synchronous circuits' tolerance to power-supply voltage and temperature oscillations, without degrading its performance. The underlying...
As IC technology scales down, power supply instability may dramatically contribute to signal integrity loss. In this paper, the authors propose a new methodology to enhance circuit tolerance to power-supply voltage (VDD1) local variations, without degrading its performance. The underlying idea is to add additional tolerance to the edge trigger of the clock signal driving specific memory cells. The...
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