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GOAHEAD is a tool for easily building complex run-time reconfigurable systems. The tool provides sophisticated features like module relocation, hierarchical reconfiguration, or reusing modules among different systems. This demonstration shows 1) how reconfigurable systems can be built using GoAhead with only a few mouse clicks. In addition, 2) we will show how a partial module can be compiled all...
In this demo, we introduce a novel architecture of an engine for high performance multi-scale detection of objects in videos based on WaldBoost training algorithm. The key properties of the architecture include processing of streamed data and low resource consumption. We implemented the engine in FPGA and we show that it can process 640 × 480 pixel video streams at over 160 FPS without the need of...
The design and development of digital electronic systems is mainly performed by use of a hardware description language. To prepare students in electrical engineering for a career in hardware design many universities provide courses on VHDL. The traditional approach in teaching VHDL is mainly by means of textbook examples and simulation provided by software applications. These exercises are perceived...
Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
The IOPT-tools Web based tool framework [1] supports the implementation of embedded systems controllers using web-based graphical tools, starting with a graphical editor to specify controller's behavior through associated Petri-net model, complemented with model-checking and system verification tools used to debug and automatically check controller behavior correctness (helping in the detection of...
Realistic benchmarks are important for FPGA Architecture and CAD evaluation. This paper provides a demo illustrating how designs described in HDL can be converted to BLIF using the Titan flow, and used in academic CAD tools.
We will demonstrate a portable FPGA tablet running a spiking neural network for handwriting recognition. The user draws digits on the tablet's touch-screen, and the neural network performs digit recognition.
Cube-1 is a heterogeneous multi-core processor which can achieve the required performance with the least energy consumption as possible. It can control the performance and energy with two levels: (1) the number of accelerators can be easily changed by increasing or decreasing the number of stacked chips after fabrication, as they are connected with inductive coupling links. (2) The supply voltage...
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