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A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in circuit design compared to the DICE cell, which...
The paper designed a power-efficient and low-cost source-series-terminated (SST) driver with 3 tap feed forward equalization (FFE) for Peripheral Component Interconnect Express (PCIe3.0), RapidIO1.3 and XAUI applications in 65nm CMOS. The proposed SST structure adopted 3 kinds of resistance slice rather than single-2.4Kohm, 1.2Kohm and 600ohm to achieve a good compromise between area, power, and impedance...
In high-speed serial communication interface circuits, a high-performance slicer is essential. This paper presents an improved slicer based on SA/FF (Sense Amplifier/Flip Flop) and extracts the sample function of whole circuit system. The results show that the proposed configuration can achieve a regeneration gain of 61.8dB and a −3dB bandwidth of 10GHz. The power consumption of the new structure...
Two 65 nm bulk CMOS test chips, each containing several different types of flip-flop chains, are designed and tested. Heavy ion results are given and analyzed across ion LET and in proposed time domain. The single event upset (SEU) and single event transient (SET) performance of various DFFs are compared and discussed, concluding several practical implications for radiation hardening by design (RHBD)...
Linear voltage regulators are widely used in electronic systems for low noise and precise output voltage. This paper presents an output-capacitorless linear voltage regulator with 5.5V∼40V input voltage, 5V output voltage and 100mA load current. The damping-factor-control (DFC) frequency compensation has effectively enhanced the loop stability. A high to low circuit is presented to supply power for...
Heavy-ion tests on 65nm CMOS Flip-Flops with different topologies are conducted to investigate their susceptibility to single event upsets (SEUs) and single event transients (SETs). The test results show that SETs on scan-enable node (SE) may cause a large number of SEUs, and the conventional delay filter is vulnerable to SETs, which can reduce the efficiency of delay-filter Flip-Flops. A new delay...
Withscaling applications in the aerospace technology of the large-scale CMOS integrated circuit, the reliability of CMOS device has been the key factor which guarantees the normal work of aerospace equipment. Due to the high-energy particles surrounding the Earth captured by the radiation belt, the CMOS circuits may be hit by them when the aerospace equipment are running around the earth, which may...
The paper simulated the SEL happening process of the CMOS inverter fabricated the 0.18um technology. The results show that the intrinsic parasitic lateral NPN (QN) and PNP (QP) transistor of the NMOS and PMOS in the CMOS inverter, which could result in the changes of the voltage and the current of the drain when the SEL happening, can delay latch up occurring time and reduce the latch up current....
This paper mainly simulated the single event latch-up (SEL) for the CMOS inverter under the 0.18um technology. The SEL of integrated circuit (IC) was also analyzed in detail. The result showed that the parasitic lateral transistors NPN and PNP of NMOS and PMOS play a role in the SEL happening process. The changes of the drain voltage and the drain current and the functional failure of the circuit...
Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit's topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicate...
In this paper, the charge collection and parasitic bipolar effect of SOI NMOS devices in case of different ion strike locations have been analyzed through 3D simulation. The simulation results show that the strike at drain region can cause charge collection comparable with the collection induced by strike at the gate region above body. Single event upset (SEU) simulations of SRAM cell have been conducted...
The 3D simulation result shows how the heavy ion strike location, the structure (with or without body contact) of the device, and the energy of strike ion affect the parasitic bipolar gain. Short distance between strike location and body contact reduces the charge collection by drain more obviously than that in the case of longer distance. The highlight of the paper lies in the discovery and analysis...
Three-dimensional TCAD simulation is used to explore a new charge-collection mechanism in highly-scaled MOSEFT. The results show the charge collection with the parasitic bipolar conduction can cause an increased SEU sensitivity. Then the problem of multiple-node upset in a 0.18μm 12-T SEU hardened SRAM cell is also studied. Unlike traditional multiple node charge collection in which diffusions near...
In this paper a single event effect (SEE) fault injection control signal generator based on Monte Carlo method is proposed. Fault control signal generated by the traditional SEE fault injection emulation method for VLSI does not take the speciality of the space environment and the electrical characteristics of the circuit into account. Whereas the signal generator presented in this paper takes advantage...
Three-dimensional simulation is used to explore the basic charge-collection mechanisms in MOSEFT. Then the problem of multiple-node upset in DICE is studied. The results show the transient floating node and charge lateral diffusion are the key reasons for MNU.
This paper presents an improved tool called FITVS (Fault Injection Tool for Validating SEE) using the FPGA-based emulation system for fault grading. A novel library-replace-modeling technique that can quickly and easily perform SEE by injecting faults into the circuit nodes is proposed. It helps IC designers to enhance the quality of their design by providing the sensitivity information of all nodes...
In this paper, a novel approach that performs device simulation in the pre-Si phase to evaluate the robustness of the ESD protection device is presented. Several key parameters, such as the spacing from gate to source contact, the spacing from gate to drain contact, the length of the gate and the width of the gate are researched using the simulator MEDICI. Tunneling phenomenon is also observed and...
In the presence of radiation, particle strikes can cause temporary signal errors in integrated circuits (ICs). Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic are called single event transients (SETs). SETs are becoming more of an issue as technology improves, as the properties that masked these faults in the past...
A new frequency compensation scheme for multistage amplifier, named capacitor-multiplier frequency compensation (CMFC), is introduced. Increasing the capacitance with a current-mode multiplier in CMFC amplifier allows the circuit to occupy less silicon area and to drive large capacitive loads more effectively. Moreover, smaller physical capacitance results in higher gain-bandwidth product (GBW) and...
Chip with four kinds of hard-by-design latches and an unhardened one is fabricated with a commercial 0.18 mum process, and tested for their SEL and SEU susceptibility. Some of the latches are tested with heavy-ions for the first time. Simulation and test results prove that the hardening methods we used are very effective. Discussions and comparisons are made among test results.
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