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In this paper, the mechanical performance of solder joints of BGA mounted on flexible printed circuit (FPC) was studied using finite element method (FEM). To optimize the electric components layout during the design, it is necessary to predict the bending reliability of components on FPC. Traditionally, 3-point or 4-point bending are common used to study if the substrate is rigid. In order to simulate...
With the increased use of mobile phones, navigation systems, PDA's, laptop's and portable gaming devices the drop reliability of microelectronics has become an important parameter. Assessing the solder interconnect quality by means of drop impact testing, as standardized by e.g. JEDEC, during normal production requires considerable amounts of time and effort. Besides this, the repeatability of the...
The increased use of mobile appliances in today's society has resulted in an increase of reliability issues related to drop performance. A common method to assess the drop performance is the JEDEC specified drop impact test [1]. In this research the solder loading is investigated by means of drop impact simulations and high-speed camera measurements. The measurements are used to enhance the simulations...
Low-Ag solder SnAgCu (SAC) is more suitable for improving the shock performance of solder joints as reported by many papers. However the properties of low-Ag solder, with different Cu contents, under service conditions are lacking. The forming mechanism of the intermetallic compound (IMC) and the relation with the joint strength need to be investigated. In this study, the effects of high-temperature...
A correlation between the drop impact test and cold bump pull test is investigated. This can be divided into three parts. First by investigating the cold bump pull test apparatus for uncontrolled parameters that might introduce a bias or spread in the results. Secondly by means of modeling the cold bump pull test to investigate solder bump deformation and solder bump loading during pull off. Finally...
A novel solder on rubber (SOR) structure of the advanced wafer level chip scaled packaging (WLCSP), having the capability of releasing the deformation energy which is caused by the CTE mismatch between the silicon chip and the substrate, is proposed herein. In the SOR structure, a metallic trace and solder pad would be formed on the rubber-based polymer, and a solder is attached onto the said pad...
A novel wafer level chip scaled packaging (WLCSP) having the capability of the redistributing the electrical circuit is proposed herein to resolve the problem of assembling a fine pitched chip to a coarse pitched substrate. In the fan-out WLCSP, the chip is first attached to a specific 8" chip carrier, and then the trench between the chips are filled by the filler polymer. The solder bumps could...
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